A Length Matching Routing Method for Disordered Pins in PCB Design Ran Zhang ,Tieyuan Pan, Li Zhu, Takahiro Watanabe Waseda University 2015 ASP.DAC

Outline Introduction Problem Definition Proposed Routing Algorithm Experimental Results Conclusions

In river routing, generally the position of pins is already fixed on the component when routing starts.

disordered

Related work The length matching problem has been proven as NP-hard Lagrangian-relaxation (a type of LP) framework was used to allocate the routing resources. a river routing based algorithm was presented to detour the net multi-layer routing problems

Different consider the routing with obstacles there are a number of obstacles, such as device and IC package a length matching routing method based on region partition transactional parallel routing algorithm routing method for disordered pins generates the optimal routes with better wire balance within reasonable CPU times

II. Problem Definition objective ：effectively assign layers for the disordered pins and generate routes with a better balance of all the nets’ length. Let C1, C2 … Cn be n components Pi be a set of pins on Ci P1 = {0, 1, 2}, P2 = {2, 3}, P3 = {0, 1, 3}, P ={0, 1, 2, 3}.

layer If there is unavoidable net crossing, another layer should be applied. simplify the problem, the components are mapped on the added layer as obstacles most three layers are permitted

topology

III. Proposed Routing Algorithm A. Layer Assignment B. Initial Routing C. Wire Length Adjustment

Layer Assignment-step1 P1, P2 … Pn is the set of pins on each component P is the set consisting of all pins Let Ps and Pt be the two sets to be merged If there are more than two sets: according to their pins’ quantities, the largest set is selected as Ps, Ps’ = P - Ps. elements shared with Ps’ most is selected as Pt

Layer Assignment-step2 Q be a set of the common elements in Ps and Pt. S be an array of elements in Q arranged in anti-clockwise order of pins on the boundary of Ps’s component. Similarly, let T be an array of elements in Q, arranged in clockwise order of pins LCS(longest common subsequence) algorithm

Initial Routing breadth first search

Greedy way

Wire Length Adjustment m*lt > [α*A], lt = [α*A/m] m: #nets; lt: target length; α: utilized coefficient; A: available routing area the adjustment of wires deals with length by even number not odd Lai = [(lt-Li)/2]*2 (Li: the current wire length of net i). If Lai is negative, we shorten the wire; otherwise, we lengthen it

補充 In recent VLSI systems, signal propagation delays are requested to achieve the specifications with very high accuracy. In order to meet the specifications, the routing of a net often needs to be detoured in order to increase the routing delay

improve

IV. Experimental Results C language by MinGW Developer Studio 2.06, on a PC with 2.66GHz Intel Core 2 CPU and 2GB RAM

V. Conclusions disordered pins in PCB design, a heuristics algorithm is proposed adjust the wire length with considering target length requirement and available routing region