Lecture 9 RX210 Introduction & I/O Ports

Outline RX Series Introduction RX210 Core RX210 Architecture RX210 Interrupt Vector Table RX210 Bus Configuration

M C U (微型) icro- (控制器) ontroller (單元) nit What is MCU? © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

RX700 RX640 RX600 RX200 RX100 RX Platform Road Map Expanding the platform at both low-end and high-end to re-enforce family concept and minimize customers’ development cost. 40nm process w/ RXv2 core (enhanced FPU and DSP) 40nm process w/ RXv2 core ( enhanced FPU and DSP ) Planning NEW Leading edge Performance Up to 4MB Flash and 512kB RAM High Performance, Integration Up to 4MB Flash and 512kB RAM WS: 2Q14 High Performance, Integration up to 2MB Flash and 256kB RAM RX700 WS: Now (120 MHz-300µA/MHz) RX640 (240 MHz) MP: Now Low power, Performance Up to 1MB Flash and 96kB RAM (100 MHz-500µA/MHz) RX600 MP: Now RX200 (50 MHz-150µA/MHz) NEW　 NEW Ultra Low power Up to 512KB MP: Now RX100 (32 MHz-110µA/MHz) © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

32bit MCU w/Low Power Consumption & High Performance Concept of RX200 Series- RX200 Series Overview High performance 32bit RX CPU 1.56DMISP/MHz Low power consumption 0.2mA/MHz Low voltage 1.62V to 5.5V Safety function IEC60730 compliant This CPU realizes lower power consumption by intermittent operation Long battery life In addition to industrial application, wide range from 1.8V portable device to 5V home appliance supported Enhance safety function of home appliance Major applications of RX200 series [Consumer] (operated by battery) 　Smartphone 　DSC/DVC [Healthcare] 　Blood pressure meter 　Glucose meter [Industrial] Power meter Pressure/temperature/ flow meter Inverter [Home appliance] Air conditioner 　Refrigerator 　Washing machine © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

Compatibility between RX210 and RX220 even RX600 series Complete compatibility between RX210and RX220! Drop-in replacement is available RX210 RX600 RX220 © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

Sample programs of middleware on the website are ready to use! Starter Kit Supports from Phase of Considering Introduction to Phase of Full-scale Development All you need for MCU evaluation and initial phase of introduction is this starter kit! CPU board, emulator (E1), Integrated Development Environment (GUI), various sample codes for MCU peripherals Sample programs of middleware on the website are ready to use! Full-scale development is possible! Code with its operation checked is used for an actual system. Bundled emulator is used for an actual system. © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

E1 offers a wide range of basic functions at a low price! Renesas On-chip Debugging Emulator 　　　　　　　　　　　　　　　　Meets Customer’s Needs Major Renesas MCU are supported. Available as Flash programmer as well. On-chip trace function is supported for some MCUs. E1 offers a wide range of basic functions at a low price! E1 ルネサス統合オンチップデバッギングエミュレータとして、低価格版E1と高機能版のE20の2種類を用意。 低価格版E1は、・・・・ 高機能版E20は、・・・・。オンチップデバッギングエミュレータでありながら従来のインサーキットエミュレータにも負けない機能を装備。 2種類のオンチップデバッギングエミュレータを組み合わせてご使用いただくことで、お客様に最適なデバッグ環境を低コストで構築可能。 © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

Environment of Flash ROM Programming: Software Succeeding software of FDT is downloadable for free! Renesas Flash Programmer New integrated Flash programming software by Renesas (Easy accessible. Suitable for development and prototype.) E1, E20 (Only E1 for RX100 series) START USB RS-232C Simple GUI specific to programming User’s system Supporting the following families: © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

RSK + E1 Check your hardware connection before debugging. © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

How to read RX datasheet There are total 42 chapter in RX210 datasheet. The description of each module is the same. Take MTU for example: © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

How to read RX datasheet There are total 42 chapter in RX210 datasheet. The description of each module is the same. Such as: © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

How to read RX datasheet There are total 42 chapter in RX210 datasheet. The description of each module is the same. Take MTU for example: © 2015 Renesas Electronics Taiwan Co.,Ltd. All rights reserved.

RX210 Core RX210 Core Properties

RX210 Core (cont.) Efficient Addressing Modes

RX210 Core (cont.) Five-Stage Pipeline: The RX CPU has 5-stage pipeline structure The RX CPU instruction is converted into one or more micro- operations, which are then executed in pipeline processing

RX210 Core (cont.) Converted into a basic single micro-operation Converted into basic multiple micro-operations

RX210 Core (cont.) Reduced Code Size

RX210 Core (cont.) Fast Interrupt Response

RX210 Registers

Sixteen general-purpose registers (R0 to R15) RX210 Registers (cont.) Sixteen general-purpose registers (R0 to R15) R1 to R15 can be used as data registers or address registers R0 also functions as the stack pointer (SP) The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) By the value of the stack pointer select bit (U) in the PSW The interrupt table register (INTB) specifies the address where the relocatable vector table starts The program counter (PC) indicates the address of the instruction being executed The processor status word (PSW) indicates the results of instruction execution or the state of the CPU The IPL[3:0] bits specify the processor interrupt priority level When the priority level of a requested interrupt is higher than the processor interrupt priority level, the interrupt is enabled

The accumulator (ACC) is a 64-bit register used for DSP instructions RX210 Registers (cont.) The following three registers are provided to speed up response to interrupts After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC register After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW The fast interrupt vector register (FINTV) specifies a branch destination address when a fast interrupt has been generated The accumulator (ACC) is a 64-bit register used for DSP instructions The ACC is also used for the multiply and multiply-and- accumulate instructions The prior value in the accumulator is modified by execution of the instruction

The RX CPU supports two processor modes Supervisor and user Enable the realization of a hierarchical CPU resource protection Each processor mode imposes a level on rights of access to the CPU resources and the instructions that can be executed Supervisor mode carries greater rights than those of user mode The initial state after a reset is supervisor mode In supervisor mode, all CPU resources are accessible and all instructions are available In user mode, write access to the CPU resources listed below is restricted Some bits (bits IPL[3:0], PM, U, and I) in the PSW Interrupt stack pointer (ISP) & Interrupt table register (INTB) Backup PSW (BPSW) & Backup PC (BPC) Fast interrupt vector register (FINTV)

Switching from user mode to supervisor mode Processor Mode (cont.) Manipulating the processor mode select bit (PM) in the processor status word (PSW) switches the processor mode Switching from user mode to supervisor mode After an exception has been generated, the PSW.PM bit is set to 0 and the CPU switches to supervisor mode The hardware pre-processing is executed in supervisor mode The state of the processor mode before the exception was generated is saved on the stack Switching from supervisor mode to user mode Executing an RTE instruction when the value of the copy of the PSW.PM bit that has been preserved on the stack is 1 Executing an RTFI instruction when the value of the copy of the PSW.PM bit that has been preserved in the BPSW is 1 The value of the stack pointer designation bit (the U bit in the PSW) becomes 1

Data Arrangement

RX210 Interrupt Vector Table Fixed Vector Table (System) Relocatable Vector Table (Peripheral) Vector numbers (from 0 to 255) are allocated to interrupt requests in a fixed way for each product

RX210 Bus Configuration CPU DTC : RAM  SFR DMA: on-chip memory external memory Introduction/Operand bus : CPU  ROM/RAM Internal main bus ½ : CPU/ROM/RAM  Peripheral Introduction bus Operand bus Bus Monitor ROM RAM DTC DMA Peripheral module DTC DMA Peripheral module Peripheral module

RX210 Bus Configuration (cont.)

RX210 Peripherals

The I/O ports function as a general I/O port Some of the pins are also configurable as an I/O pin of a peripheral module or an input pin for an interrupt All pins function as input pins immediately after a reset Pin functions are switched by register settings The setting of each pin is specified by the registers for the corresponding I/O port and on-chip peripheral modules Each port has: The port direction register (PDR) selects input or output direction The port output data register (PODR) holds data for output The port input data register (PIDR) indicates the pin states The open drain control register y (ODRy, y = 0, 1) selects the output type of each pin The pull-up control register (PCR) controls on/off of the input pull-up MOS

I/O Ports (cont.) The driving ability control register (DSCR) selects the driving ability The port mode register (PMR) specifies the pin function of each port

I/O Ports (cont.)

Port Direction Register (PDR) Register Description Port Direction Register (PDR) Used to select the input or output direction for individual pins of the corresponding port m when the pins are configured as the general I/O pins

Register Description (cont.) Port Output Data Register (PODR) Holds the data to be output from the pins used for general output ports

Register Description (cont.) Port Input Data Register (PIDR) Indicates individual pin states of port m

Register Description (cont.) Open Drain Control Register 0

Register Description (cont.) Open Drain Control Register 1

Register Description (cont.) Drive Capacity Control Register (DSCR) The bit corresponding to a pin with the fixed drive capacity can be read from or written to The drive capacity cannot be changed When a transition to deep software standby mode is made, all bits are set to normal drive output Also set to normal drive output after canceling the mode When high-drive output is selected, switching noise increases compared to when normal output is selected Carefully evaluate the effect of noise on the MCU caused by adjacent pins before selecting high-drive output

Multi-Function Pin Controller (MPC) The multi-function pin controller (MPC) is used to allocate input and output signals for peripheral modules and input interrupt signals to pins from among multiple ports Also used to allocate external-bus related signals to port pins Write-Protect Register (PWPR) PFSWE Bit (PFS Register Write Enable): Writing to PmnPFS register is enabled only when the PFSWE bit is set to 1 B0WI Bit (PFSWE Bit Write Disable): Writing to the PFSWE bit is enabled only when the B0WI bit is set to 0

Register Description P0n Pin Function Control Register (P0nPFS) (n = 0 to 3, 5, 7)

Register Description (cont.) P1n Pin Function Control Registers (P1nPFS) (n = 2 to 7)

Register Description (cont.) CS Output Enable Register (PFCSE)

Register Description (cont.) Address Output Enable Register 0 (PFAOE0)

Register Description (cont.) Address Output Enable Register 1 (PFAOE1)

Register Description (cont.) External Bus Control Register 0 (PFBCR0)

Register Description (cont.) External Bus Control Register 1 (PFBCR1)