Processor Design Computer Architecture CS 215 Updated 10/21/14

Registers  Special purpose registers  Accumulators (arithmetic registers)  Status register

Machine Types  Accumulator machines Limited number of data accumulators 1-address machines  Stack machines No register names Registers organized as a stack 0-address machine  General register machines Most often used today Registers used for almost any purpose

Instruction Sets  Each family of CPUs has its own instruction set  Instruction codes are mapped to instructions Data movement Arithmetic Logic Control

Instructions  Must contain … Which operation to perform Where to find the operand(s), if any Where to put the result, if any Where to find the next instruction

Memory Access  Each register has a unique address  Two operations Read Write

Memory Access: Read  CPU places an address on the address bus, and a read request on the control bus  Memory unit receives request, decodes address, and locate data at address  Memory unit places data on data bus  Memory unit places a complete message on control bus

Memory Access: Write  CPU places an address on the address bus, value to be written on data bus, and a write request on the control bus  Memory unit receives request, decodes address  Memory unit stores data at address  Memory unit places a complete message on control bus

Addressing Modes  Immediate i  Direct M[i]  Indirect M[M[i]]  Register direct R[i]  Register indirect M[R[i]]  Displacement M[R[i]+c]]  Relative M[PC+c]

SRC Instructions  Load instructions ld, ldr, la, lar  Store instructions st, str  Arithmetic add, addi, sub, neg  Logic and, andi, or, ori, not shr, sha, shl, shc  Branching br, brl  Miscellaneous nop, stop

Instruction Formats Oprarbc2 ld, st, la, addi, andi, ori Oprac1 ldr, str, lar

Instruction Formats Opraunused neg, not Opunused(c3) unused br rc rbrcCond

Instruction Formats Opraunused add, sub, and, or rbrc Opra(c3) unused brl rbrcCond

Instruction Formats Opunused nop, stop Opra(c2) unused shr, shra, shl, shc rbCount Opra(c3) unusedrbrc00000

Example: cnt:.equ 8.org0 seq:.dc1 next:.dc1 ans:.dwcnt.org0x1000 larr31,loop lar0,cnt lar1,seq loop:ldr2,seq(r1) ldr3,next(r1) addr2,r2,r3 str2,ans(r1) addir1,r1,4 addir0,r0-1 brnzr31,r0 stop

Try this!  Develop instruction formats for a 16-bit CPU, which has 16, 16-bit general purpose registers.

CPU Design  Control Unit Generates the control signals in the correct order to effect the correct data path activity  Data Path Set of interconnections and auxiliary registers Needed to accomplish overall changes an instruction makes CPU Control Unit Data Path Control signals out Control unit inputs

Register Transfer Notation  Provides a formal means of describing machine structure and function  Is at the “just right” level for machine descriptions  Does not replace hardware description languages.  Can be used to describe what a machine does (an Abstract RTN) without describing how the machine does it.  Can also be used to describe a particular hardware implementation (A Concrete RTN)

RTN (Cont’d.)  At first you may find this “meta description” confusing, because it is a language that is used to describe a language.  You will find that developing a familiarity with RTN will aid greatly in your understanding of new machine design concepts.  We will describe RTN by using it to describe SRC.

Static Properties  Specifying registers IR   specifies a register named “IR” having 32 bits numbered 31 to 0  “Naming” using the := naming operator: op  4..0  := IR   specifies that the 5 msbs of IR be called op, with bits Notice that this does not create a new register, it just generates another name, or “alias” for an already existing register or part of a register.

Dynamic Properties Conditional expressions: (op=12)  R[ra]  R[rb] + R[rc]: ; defines the add instruction “if” condition “then” RTN Assignment Operator This fragment of RTN describes the SRC add instruction. It says, “when the op field of IR = 12, then store in the register specified by the ra field, the result of adding the register specified by the rb field to the register specified by the rc field.”

Register Declarations  General register specifications shows some features of the notation  Describes a set of bit registers with names R[0] to R[31] R[0..31]   : Name of registers Register # in square brackets.. specifies a range of indices msb # lsb# Bit # in angle brackets Colon separates statements with no ordering

Naming Operator  Defining names with formal parameters is a powerful formatting tool  Used here to define word memory (big endian) M[x]   := Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]: Dummy parameter Naming operator Concatenation operator All bits in register if no bit index given

Memory  Processor State PC :  32-bit register Program Counter IR :  32-bit register Instruction Register Run:  1-bit run/halt indicator Strt:  Start signal R[0..31] :  32, 32-bit general purpose registers

Main Memory Mem[ ] : 2 32 addressable bytes of memory M[x] : = Mem[x]#Mem[x+1]#Mem[x+2]#Mem[x+3]:

Instruction Formats op : = IR Operation code field ra : = IR Target register field rb : = IR Operand, address index, or branch target register rc : = IR Second operand, conditional test, or shift count register

Instruction Formats c1 : = IR Long displacement field c2 : = IR Short displacement or immediate field c3 : = IR Count or modifier field

Effective Address Calculations  Displacement disp :=((rb=0)  c2 {sign extend}: (rb  0)  R[rb]+c2 {sign extend, 2’s compliment}):  Relative rel :=PC +c1 {sign extend, 2’s comp}:

Instruction Interpretation & Execution instruction_interpretation:=(  Run  Strt  (Run  1: instruction_intepretation): Run  (IR  M[PC]:PC  PC+4: instruction_execution): ):

Load & Store Instructions instruction_execution:=( ld(:=op=1)  R[ra]  M[disp]: load register ldr(:=op=2)  R[ra]  M[rel]: load register relative st(:=op=3)  M[disp]  R[ra]: store register str(:=op=4)  M[rel]  R[ra]: store register relative la(:=op=5)  R[ra]  disp: load displacement address lar(:=op=6)  R[ra]  rel: load relative address

Branch Instruction cond:=(c3 =0  0:Never c3 =1  1:Always c3 =2  R[rc]=0:Register=0 c3 =3  R[rc]  0 :Register  0 c3 =4  R[rc] =0:>= 0 c3 =5  R[rc] =1):< 0 br(:=op=8)  (cond  PC  R[rb]):Cond branch brl(:=op=9)  (R[ra]  PC:Branch & link cond  (PC  R[rb])):

ALU Instructions  Arithmetic Instructions add(:=op=12)  R[ra]  R[rb]+R[rc]: addi(:=op=13)  R[ra]  R[rb]+c2 : sub(:=op=14)  R[ra]  R[rb]-R[rc]: neg(:=op=15)  R[ra]  -R[rc]:

ALU Instructions  Logical Operations and(:=op=20)  R[ra]  R[rb]  R[rc]: andi(:=op=21)  R[ra]  R[rb]  c2 : or(:=op=22)  R[ra]  R[rb]  R[rc]: ori(:=op=23)  R[ra]  R[rb]  c2 : not(:=op=24)  R[ra]  R[rc]:

ALU Instructions  Shift Operations n:=((c3 =0)  R[rc] : (c3  0)  c3 ): shr(:=op=26)  R[ra]  : shra(:=op=27)  R[ra]  )#R[rb] : shl(:=op=28)  R[ra]  R[rb] shc(:=op=29)  R[ra]  R[rb] #R[rb]

Miscellaneous Instructions nop(:=op=0)  :No operation stop(:=op=31)  run  0):Stop instruction instruction_interpretation:End of instr_execution; invoke instr_interpretation

Abstract vs. Concrete RTN  Abstract: What occurs R[3]  R[1] + R[2];  Concrete: How it occurs Y  R[2]; Z  R[1] + Y; R[3]  Z;  Control Sequence R[2] out, Y in ; R[1] out, Z in ; Z out, R[3] in ;

Bus Transfers The Rules of Buses 1. Only one item can be on the bus during a given clock cycle. 2. The contents of the bus disappear at the end of the clock cycle. No information is “stored” on the bus from cycle to cycle; any value to be saved must be stored into a register at the end of the clock cycle.

Clock Cycle

1-Bus Microarchitecture  Only one value can be placed on the bus at any time

Abstract Vs. Concrete RTN  How would you accomplish the following instruction using this architecture? add(:=op=12)  R[ra]  R[rb]+R[rc]:

Abstract Vs. Concrete RTN add(:=op=12)  R[ra]  R[rb]+ R[rc]: StepRTN

Abstract Vs. Concrete RTN: addi StepRTN T0.MA  PC: C  PC + 4; T1.MD  M[MA]; PC  C; T2.IR  MD; T3.A  R[rb]; T4.C  A + c2 {sign ext.}; T5.R[ra]  C;

Abstract Vs. Concrete RTN: ld StepRTN T0-T2 Instruction fetch T3.A  (rb=0  0: rb  0  R[rb]); T4.C  A + #IR ); T5.MA  C; T6.MD  M[MA]; T7.R[ra]  MD;

Abstract Vs. Concrete RTN: st StepRTN T0-T2 Instruction fetch T3.A  (rb=0  0: rb  0  R[rb]); T4.C  A + #IR ); T5.MA  C; T6.MD  R[ra]; T7.M[MA]  MD;

Abstract Vs. Concrete RTN: br StepRTN T0-T2 Instruction fetch T3.CON  cond(R[rc]); T4.CON  PC  R[rb];

Abstract Vs. Concrete RTN: shr StepConcrete RTN T0-T2 Instruction fetch T3.n  IR ; T4.(n=0)  (n  R[rc] ; T5.C  R[rb]; T6.Shr (:= (n≠0)  (C  0#C : n  n-1; Shr) ); T7.R[ra]  C;

More Detail …

ra, rb, rc fields General purpose registers Control signals 5x32 decoder

Try this!  Problem Extend the SRC instruction set by adding the XOR command (op=19), similar to the AND command Note: The ALU cannot be altered by adding XOR Develop both an abstract and concrete RTN for the instruction

Try this!

Instruction Register Sign extension

Memory Interface From bus From memory To memory To bus

ALU

Control sequences: Instruction Fetch StepConcrete RTNControl Sequence T0.MA  PC: C  PC+4;PC out, MA in, Inc4, C in T1.MD  M[MA]: PC  C;Read, C out, PC in, Wait T2.IR  MD;MD out, IR in T3.Instruction_execution

Control sequences: add StepConcrete RTNControl Sequence T0.MA  PC: C  PC+4;PC out, MA in, Inc4, C in, Read T1.MD  M[MA]: PC  C;C out, PC in, Wait T2.IR  MD;MD out, IR in T3.A  R[rb];Grb, R out, A in T4.C  A + R[rc];Grc, R out, ADD, C in T5.R[ra]  C;C out, Gra, R in, End

Control sequences: addi StepConcrete RTNControl Sequence T0.MA  PC: C  PC + 4; PC out, MA in, Inc4, C in T1.MD  M[MA]; PC  C;C out, PC in, Wait, Read T2.IR  MD;MD out, IR in T3.A  R[rb];Grb, R out, A in T4.C  A + c2   {sign ext.};c2 out, ADD, C in T5.R[ra]  C;C out, Gra, R in, End

Control sequences: st StepConcrete RTNControl Sequence T0-T2Instruction fetch Instruction fetch T3.A  (rb=0)  0: rb  0  R[rb];Grb, BA out, A in T4.C  A + c2   {sign ext.};c2 out, ADD, C in T5.MA  C;C out, MA in T6.MD  R[ra];Gra, R out, MD in, Write T7.M[MA]  MD;Wait, End } address arithmetic

Control sequences: shr StepConcrete RTNControl Sequence T0-T2Instruction fetchInstruction fetch T3.n  IR  4..0  ;c1 out, Ld T4.(n=0)  (n  R[rc]  4..0  );n=0  (Grc, R out, Ld) T5.C  R[rb];Grb, R out, C=B, C in T6.Shr (:=(n≠0)  n  0  (C out, SHR, C in, (C    0#C   :Decr, Goto6) n  n-1; Shr) ); T7.R[ra]  C;C out, Gra, R in, End

Control sequences: br StepConcrete RTNControl Sequence T0-T2Instruction fetchInstruction fetch T3.CON  cond(R[rc]);Grc, R out, CON in T4.CON  PC  R[rb];Grb, R out, CON  PC in, End

Clocking & Timing

Control Unit

2-Bus SRC

3-Bus SRC

Machine Reset  From a need to initialize processor to a known, defined state Control Step Counter  0 PC  Known Value  RTN instruction_interpretation := (  Run  Strt  (Run  1: PC, R[0..31]  0); Run  Rst (IR  M[PC]: PC  PC + 4; instruction_execution): Run  Rst  ( Rst  0: PC  0); instruction_interpretation):

Exceptions  Different from branches and jumps  Resolved in the writeback stage

Exceptions  When detected … Following instructions (earlier in the pipeline) are marked as invalid As they flow to the end of the pipe their results are discarded Program counter is set to the address of a special exception handler Special registers are written with the exception location and cause

Exceptions  Types: System Reset Machine Check Exceptions  Memory error checking Data Access Exceptions Instruction Access Exceptions Alignment Exceptions

Program Exceptions  Illegal instruction  Unimplemented instruction  Privileged instruction  Arithmetic errors (sometimes)

Other Exceptions  Miscellaneous Hardware Exceptions Countdown to zero  Trace & Debugging Exceptions  Nonmaskable Exceptions Cannot be ignored Power outage  Interrupts (External)

Exception Process  Interrupt signal asserted  Determine if interrupt should be serviced; Finish current instruction, if possible

Exception Process instruction_interpretation := (  Run  Strt  Run  1: Run  (ireq  IE)  (IR  M[PC]: PC  PC + 4; instruction_execution): Run  (ireq  IE)  (IPC  PC   : II    Isrc_info   : iack  1: IE  0: PC  Ivect   ; iack  0); instruction_interpretation);