© 2000 Prentice Hall Inc. Figure 12.1 Circuit symbol for the comparator. If v 1 > v 2, then v o is high; if v 1 < v 2, then v o is low.

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Presentation transcript:

© 2000 Prentice Hall Inc. Figure 12.1 Circuit symbol for the comparator. If v 1 > v 2, then v o is high; if v 1 < v 2, then v o is low.

© 2000 Prentice Hall Inc. Figure 12.2 Transfer characteristics of ideal comparators.

© 2000 Prentice Hall Inc. Figure 12.3 Transfer characteristic of a real comparator.

© 2000 Prentice Hall Inc. Figure 12.4 The LM111 has an open-collector output.

© 2000 Prentice Hall Inc. Figure 12.5 The input voltage v in is compared to the reference voltage V r.

© 2000 Prentice Hall Inc. Figure 12.6 Noise added to the input signal can cause undesired transitions in the output signal.

© 2000 Prentice Hall Inc. Figure 12.7 A Schmitt trigger is formed by using positive feedback with a comparator.

© 2000 Prentice Hall Inc. Figure 12.8 Noninverting Schmitt trigger.

© 2000 Prentice Hall Inc. Figure 12.9 Schmitt triggers that can be designed to have specified thresholds.

© 2000 Prentice Hall Inc. Figure Schmitt trigger designed in Example 12.1.

© 2000 Prentice Hall Inc. Figure Input voltage and output voltage versus time for the circuit of Figure

© 2000 Prentice Hall Inc. Figure Transfer characteristic for the Schmitt trigger of Example12.1.

© 2000 Prentice Hall Inc. Figure Answer for Exercise12.1.

© 2000 Prentice Hall Inc. Figure Answer for Exercise 12.2.

© 2000 Prentice Hall Inc. Figure Answer for Exercise 12.3.

© 2000 Prentice Hall Inc. Figure 12.16a Astable multivibrator.

© 2000 Prentice Hall Inc. Figure 12.16b Astable multivibrator.

© 2000 Prentice Hall Inc. Figure Waveforms of Figure 12.16b with t = 0 at the start of a positive half-cycle of v o (t).

© 2000 Prentice Hall Inc. Figure Astable multivibrator designed in Example 12.3.

© 2000 Prentice Hall Inc. Figure Simulated voltages for the circuit of Figure

© 2000 Prentice Hall Inc. Figure Circuit for Exercise 12.5.

© 2000 Prentice Hall Inc. Figure Answer for Exercise 12.5b.

© 2000 Prentice Hall Inc. Figure Circuit for Exercise 12.6.

© 2000 Prentice Hall Inc. Figure Answer for Exercise 12.6b.

© 2000 Prentice Hall Inc. Figure Simplified functional block diagram of 555 timer IC.

© 2000 Prentice Hall Inc. Figure Monostable multivibrator.

© 2000 Prentice Hall Inc. Figure Astable oscillator.

© 2000 Prentice Hall Inc. Figure Circuit for Exercises 12.7 and 12.8.

© 2000 Prentice Hall Inc. Figure Simple rectifier circuits such as this are not suitable for precision rectification of small-amplitude ac signals.

© 2000 Prentice Hall Inc. Figure 12.29a Precision half-wave rectifier.

© 2000 Prentice Hall Inc. Figure 12.29b Precision half-wave rectifier.

© 2000 Prentice Hall Inc. Figure Improved half-wave rectifier.

© 2000 Prentice Hall Inc. Figure Precision full-wave rectifier.

© 2000 Prentice Hall Inc. Figure See Exercise

© 2000 Prentice Hall Inc. Figure Simple peak detector.

© 2000 Prentice Hall Inc. Figure Precision peak detector.

© 2000 Prentice Hall Inc. Figure Answers for Exercise

© 2000 Prentice Hall Inc. Figure 12.36a Sample-and-hold circuit.

© 2000 Prentice Hall Inc. Figure 12.36b Sample-and-hold circuit.

© 2000 Prentice Hall Inc. Figure 12.37a Precision clamp circuit.

© 2000 Prentice Hall Inc. Figure 12.37b Precision clamp circuit.

© 2000 Prentice Hall Inc. Figure 12.38a Answers for Exercise

© 2000 Prentice Hall Inc. Figure 12.38b Answers for Exercise

© 2000 Prentice Hall Inc. Figure Analog-to-digital conversion.

© 2000 Prentice Hall Inc. Figure The DAC output is a staircase approximation to the original signal. Filtering removes the sharp corners. (Note: In addition to smoothing, the filter delays the signal. The delay is not shown.)

© 2000 Prentice Hall Inc. Figure Circuit symbol for a digital-to-analog converter.

© 2000 Prentice Hall Inc. Figure DACs can be implemented using a weighted-resistance network. (Note: If d i = 1, the corresponding switch is to the right-hand side. For d i = 0, the i th switch is to the left-hand side.)

© 2000 Prentice Hall Inc. Figure An R -- 2R ladder network. The resistance seen looking into each section is 2R. Thus, the reference current splits in half at each node.

© 2000 Prentice Hall Inc. Figure An n-bit DAC based on the R–2R ladder network.

© 2000 Prentice Hall Inc. Figure A practical n-bit DAC based on BJT technology that uses emitter-coupled pairs as current switches.

© 2000 Prentice Hall Inc. Figure 12.46a Switched-capacitance DACs.

© 2000 Prentice Hall Inc. Figure 12.46b Switched-capacitance DACs.

© 2000 Prentice Hall Inc. Figure Conceptual block diagram of an analog-to-digital converter.

© 2000 Prentice Hall Inc. Figure A flash converter.

© 2000 Prentice Hall Inc. Figure Output versus input for a 3-bit ADC.

© 2000 Prentice Hall Inc. Figure 12.50a Dual-slope ADC.

© 2000 Prentice Hall Inc. Figure 12.50b Dual-slope ADC.

© 2000 Prentice Hall Inc. Figure 12.51a Successive approximation ADC.

© 2000 Prentice Hall Inc. Figure 12.51b Successive approximation ADC.