Fundamentals of Digital Logic B. Furman 25NOV2014

Mechatronics Concept Map System to Control Sensor Signal Conditioning Controller (Hardware & Software) Power Interface Actuator User Interface Power Source BJ Furman 26JAN06 ME 106 ME 154 ME 157 ME 195 ME 120 ME 297A ME 106 ME 120 ME 106 ME 190 ME 187 ME 110 ME 136 ME 154 ME 157 ME 182 ME 189 ME 195 ME 106 ME 120 ME 106 EE 118 INTEGRATION

Digital Logic Combinatorial Logic  The combination of logic states (0’s and 1’s) at the inputs of logic gates (digital logic elements) determines the output state according to the logic function. AND, OR, NOT, XOR NAND, NOR  Ex BCD-to-7-segment decoder; ‘enable’ inputs Ex BCD-to-7-segment decoder; ‘enable’ inputs Sequential Logic  The combination of input logic states and their sequencing determines the output state Flip-flops  Ex. Computer memory, microcontroller registers

Review of Logic Functions AND, OR, NOT, XOR, NAND, NOR

Truth Tables for Logic Functions Logic FunctionOR ABZ Logic FunctionAND ABZ Logic FunctionNOR ABZ Logic FunctionNAND ABZ Logic FunctionNOT AZ Logic FunctionXOR ABZ

Boolean Algebra Laws and Identities See the handout

All logic functions can be formed from NAND or NOR gates alone

Demorgan’s Theorem You can swap shapes (AND or OR), if at the same time you invert all inputs and outputs.

Combinatorial Logic The three logic functions, AND, OR, and NOT can be used to build any digital device NAND gates or NOR gates are universal, i.e., can be used to construct the three logic functions, hence any digital device  Ex. Z A

Internal Construction – Inverter (TTL) (Source: inputoutput Logic FunctionNOT AZ AZ

Inverter Operation Input High (1)Input Low (0) 5 V 0 V (Source:

CMOS Inverter

Logic Chips - c. 1960’s and 1970’s Multi-input versions exist  Examples: 7421 Dual 4-input AND 74LS00 Quad 2-input NAND

Logic Chips c – pres. Programmable logic devices (PLD)  Programmable Array Logic (PAL)  Generic Array Logic (GAL) Lattice Semiconductor c Erasable and reprogrammable PAL device  Complex Programmable Logic Device (CPLD) More gates than PALs and GALS  Field Programmable Gate Array (FPGA)

Field Programmable Gate Array (FPGA) A ‘programmable’ digital logic device  You define the logic functions in a Hardware Descriptor Language (HDL)  Compile the HDL description into a binary file  Download the binary to the FPGA device  Voila! You have a device that will execute your logic function For more information: 

Combinatorial Logic Circuit Design Vote counting circuit

Digital Logic Families See the handout

Sequential Logic Output based on input values and their sequencing  timing is important!  Will often use trigger signals, called ‘clock’ (Clk) signals to trigger events Flip-Flops (also known as bi-stables or latches)  Devices that can store and switch between binary states, 0 and 1  Fundamental building block of all semiconductor memory and processing in digital computers  Made up of logic gates with feedback (some outputs are fed back to inputs of other gates)

R-S Flip-Flop S stand for ‘set’ R stands for ‘reset’ Q and Qbar are complementary outputs t prop is the ‘ propagation delay time ’, which is the time it takes the logic gate to change its output state following a change in the state of the input. InputsOutputs SRQ 00Q 0 (1) (0) NA R SQ NA means ‘not allowed’ R S Q R S t prop (inverter) t prop (NAND) Time Q t prop (NAND)

Triggering Flip-Flops Often important to synchronize changes on a clock signal Types of clock signals to trigger on:  Level (no ‘wedge’ symbol. If no bubble, active HIGH. With bubble, active LOW)  Negative edge (bubble+wedge): 1  0 transition  Positive edge (wedge): 0  1 transition InputsClkOutputs SR  Q 00  Q0Q0 10   01 11NA R SQ Clk NA means ‘not allowed’  means activated on rising edge of clock signal (positive edge) Negative Edge-Triggered R-S Flip-Flop Active-HIGH (level triggered) R-S Flip-FlopActive-LOW (level triggered) R-S Flip-Flop

Other Types of Flip-Flops - 1 D Flip-Flop (ex. 7474) Clk DQ Preset Clear PresetClearDClkQ 110   10 11x0Q0Q0 11x1Q0Q0 01xx10 10xx01 00xxNA Single input is stored and presented to Q on edge of clock pulse Ex. Positive edge- triggered D flip-flop Preset pulled low (“active low”) will set Q to 1 Clear pulled low (“active low”) will clear or reset Q to 0 Scherz, Practical Electronics for Inventors, p. 688 What are ‘preset’ and ‘clear’? Truth Table

Other Types of Flip-Flops - 2 JK Flip-Flop (ex. 7476) Clk JQ Preset Clear K PresetClearJKClkQ 1100  Q0Q    Toggle 11xx0, 1Q0Q0 01xxx10 10xxx01 00xxxNA Positive edge-triggered JK flip-flop Like RS flip-flop, where J is like S and K is like R, but can have both J and K high. This will cause output to toggle (change state) Scherz, Practical Electronics for Inventors, p. 692 Truth Table

Sequential Logic Applications - 1 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2 nd ed., McGraw-Hill, NY.

Sequential Logic Applications - 2 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2 nd ed., McGraw-Hill, NY.

Sequential Logic Applications - 3 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2 nd ed., McGraw-Hill, NY. PresetClearJKClkQ 1100  Q0Q    Toggle 11xx0, 1Q0Q0 01xxx10 10xxx01 00xxxNA

Sequential Logic Applications - 4 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2 nd ed., McGraw-Hill, NY. A ‘T’ flip-flop is essentially a JK flip-flop with J and K inputs tied HIGH and the clock input tied to the T input

555 Timer IC See handout  Uses a flip-flop  Many applications Precision timing Pulse generation Sequential timing Time delay generation PWM

7447 BCD to 7-segment Decoder