Fall 2008EE VLSI Design I - © Kia Bazargan 1 EE 5323 – VLSI Design I Kia Bazargan University of Minnesota Adders

Fall 2008EE VLSI Design I - © Kia Bazargan 2 References and Copyright Textbooks referenced  [WE92] N. H. E. Weste, K. Eshraghian “Principles of CMOS VLSI Design: A System Perspective ” Addison-Wesley, 2 nd Ed.,  [Rab96] J. M. Rabaey “Digital Integrated Circuits: A Design Perspective ” Prentice Hall,  [Par00] B. Parhami “Computer Arithmetic: Algorithms and Hardware Designs ” Oxford University Press, 2000.

Fall 2008EE VLSI Design I - © Kia Bazargan 3 References and Copyright (cont.) Slides used  [©Hauck] © Scott A. Hauck, ; G. Borriello, C. Ebeling, S. Burns, 1995, University of Washington  [©Prentice Hall] © Prentice Hall 1995, © UCB 1996 Slides for [Rab96]  [ ©Oxford U Press] © Oxford University Press, New York, 2000 Slides for [Par00] With permission from the author

Fall 2008EE VLSI Design I - © Kia Bazargan 4 Why Adders? Addition: a fundamental operation  Basic block of most arithmetic operations  Address calculation Faster, faster and faster How?  Architectural level optimization  Gate-level optimization  Speed/area trade-off

Fall 2008EE VLSI Design I - © Kia Bazargan 5 Outline One-bit adder, basic ripple-carry adder Carry-Lookahead adders (CLA) Brent-Kung adder

Fall 2008EE VLSI Design I - © Kia Bazargan 6 One-bit Half Adder: One-bit Full Adder: Adding Two One-bit Operands Sum = A  B  Cin Cout = A.B + B.Cin + A.Cin FA AB C in C out Sum Sum = A  B Cout = A.B HA AB C out Sum A B Sum Cout C in A B Sum Cout

Fall 2008EE VLSI Design I - © Kia Bazargan 7 N-Bit Ripple-Carry Adder: Series of FA Cells To add two n-bit numbers C0C0 FA A0A0 S0S0 B0B0 A1A1 S1S1 B1B1 A2A2 S2S2 B2B2 A n-1 S n-1 B n-1 CnCn... Note: adder delay = Tc * n Tc = (C in :C out delay) FA AB CinCin C ou t Sum

Fall 2008EE VLSI Design I - © Kia Bazargan 8 4-bit Ripple Carry Addition: Example C0C0 FA A0A0 S0S0 B0B0 A1A1 S1S1 B1B1 A2A2 S2S2 B2B2 A3A3 S3S3 B3B3 C4C4 C1C1 C2C2 C3C3 T= T=0 B=0101 A=0011 S=0000 S= T=2 S= T=3 S= T=4 S=1000

Fall 2008EE VLSI Design I - © Kia Bazargan 9 One-bit Full Adder Implementation Direct gate implementation Cout = A.B + B.Cin + A.Cin = A.B + Cin. (A+B) Sum = A  B  Cin A B Cin Sum A B A B Cin Cout 32 Transistors Used [WE92] p516

Fall 2008EE VLSI Design I - © Kia Bazargan 10 includes 111 excludes 000 One-Bit Full Adder: Share Logic An observation  Almost always, sum = NOT carry C in A B Sum Cout Sum = A.B.Cin + (A+B+Cin).Cout

Fall 2008EE VLSI Design I - © Kia Bazargan 11 One-Bit Full Adder: Transistor Implementation Sum = A.B.C + (A+B+C).Cout Cout = A.B + C.(A+B) A B B A C A B AB C Cout C B A A B C C B A C BA Sum –Use inverters to get Cout and Sum –C transistors close to output –Cout delay: 2 inverting stages (1-stage possible?) –Sum delay: 3 inverting stages (not an issue, though) 28 Transistors [WE92] p517 [Rab96] p390

Fall 2008EE VLSI Design I - © Kia Bazargan 12 Outline One-bit adder, basic ripple-carry adder Carry-Lookahead adders (CLA) Brent-Kung adder

Fall 2008EE VLSI Design I - © Kia Bazargan 13 Carry-Lookahead Adder: Idea New look: carry propagation Idea:  Try to “predict” C k earlier than T c *k  Instead of passing through k stages, compute C k separately using 1-stage CMOS logic Carry propagation: an example Bit position Carry A B Sum

Fall 2008EE VLSI Design I - © Kia Bazargan 14 0-propagate 1-propagategenerate kill (kill) (propagate) (generate) Carry-Lookahead Adder (CLA): One Bit What happens to the propagating carry in bit position k? C C 1 0 C C C A A B B A A B B Cout [Rab96] p391 p = A+B (or A  B) g = A.B A B C in Cout

Fall 2008EE VLSI Design I - © Kia Bazargan 15 CLA: Propagation Equations If C 4 =1, then either:  g 3 generated at bit pos 3  g 2.p 3 generated at bit pos 2, propagated 3  g 1.p 2.p 3 generated at bit pos 1, propagated 2,3  g 0.p 1.p 2.p 3 generated at bit pos 0, propagated 1,2,3  C in.p 0.p 1.p 2.p 3 input carry, propagated 0,1,2,3 C 4 = g 3 + g 2.p 3 + g 1.p 2.p 3 + g 0.p 1.p 2.p 3 + C in.p 0.p 1.p 2.p 3 Implement C 4 as a one-stage CMOS logic  large delay

Fall 2008EE VLSI Design I - © Kia Bazargan 16 CLA: 12-Bit Example T= B= A= T= T= T=4

Fall 2008EE VLSI Design I - © Kia Bazargan 17 Summary: Carry Lookahead Adder CLA compared to ripple-carry adder:  Faster (“4 times”?), but delay still linear (w.r.t. # of bits)  Larger area oP, G signal generation oCarry generation circuits oCarry generation ckt for each bit position (no re-use) Limitation: cannot go beyond 4 bits of look-ahead  Large p,g fan-out slows down carry generation

Fall 2008EE VLSI Design I - © Kia Bazargan 18 Outline One-bit adder, basic ripple-carry adder Carry-Lookahead adders (CLA) Brent-Kung adder

Fall 2008EE VLSI Design I - © Kia Bazargan 19 Binary Carry-Lookahead or Brent-Kung Adder Idea: use binary tree for carry propagation  logarithmic delay A 7 F A 6 A 5 A 4 A 3 A 2 A 1 A 0 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 F t p  log 2 (N) t p  N [© Prentice Hall]

Fall 2008EE VLSI Design I - © Kia Bazargan 20 Brent-Kung Adder Basic component Concatenation MSBLSB g left p left g right p right g p (g, p) g = g left + p left g right p = p left p right (g left, p left )  (g right p right ) [©Hauck]

Fall 2008EE VLSI Design I - © Kia Bazargan 21 No! Doesn’t know about C 0-3 yet! C5?C5? Brent-Kung Adder: Structure Define (Gi, Pi)  generate and propagate for least significant i bits (G 0,P 0 ) = (g 0,p 0 )g i = A i.B i p i = A i  B i for i>0: (G i, P i ) = (g i, p i ) (G i-1, P i-1 ) = (g i, p i ) (g i-1, p i-1 ).... (g 1, p 1 ) Key to Brent-Kung adder – use tree structure to perform concatenations [©Hauck]

Fall 2008EE VLSI Design I - © Kia Bazargan 22 Brent-Kung: the Complete Tree t add  log 2 (N) [© Prentice Hall] (g 0,p 0 ) (g 1,p 1 ) (g 2,p 2 ) (g 3,p 3 ) (g 4,p 4 ) (g 5,p 5 ) (g 6,p 6 ) (g 7,p 7 ) C 0 C 1 C 3 C 7 C 2 C 6 C 5 C 4

Fall 2008EE VLSI Design I - © Kia Bazargan 23 Brent-Kung: Timing [©Oxford U Press] [Par00] p.102 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s Level

Fall 2008EE VLSI Design I - © Kia Bazargan 24 Brent-Kung Adder: Summary Area  On average, twice as large as ripple adder  Layout of the cells is very compact Delay  Logarithmic time  Once carry signals are ready, sum bits derived in const time  Good for wide adders