Digital Integrated Circuits A Design Perspective EE141 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003

What is this course all about? What will you learn? Understanding, designing, and optimizing digital integrated circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability Difference from previous courses: Digital circuit design at lowest design level (transistor, layout and manufacturing level) Integrated Circuit (IC) Extensive use of CAD tools

Digital Integrated Circuits Introduction: Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing issues Arithmetic building blocks VLSI CAD

Introduction Why is designing digital ICs different today than it was before? Will it change in future?

The First Computer

The first electronic computer (1946)

The Transistor Revolution First transistor Bell Labs, 1948

The First Integrated Circuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966

Basic IC circuit component: MOS transistor MOS: Metal Oxide Semiconductor

Intel 4004 Micro-Processor 1971 1000 transistors < 1MHz operation 10μm technology

Intel Pentium (IV) microprocessor 2001 42 Million transistors 1.5 GHz operation 0.18μm technology

Intel Core™2 Duo Processor 2006 291 Million transistors 3 GHz operation 65nm technology

More recent Processors 2007 800 Million transistors 2 GHz operation 45nm technology (the biggest change in CMOS transistor technologies in 40 years) 2010 Core i7 1.2 Billion transistors 3.3 GHz operation 32nm technology 2012 Core i7 (newer generations) 1.7 Billion transistors 4.0 GHz operation 22nm technology 14nm in 2015, and then 10nm, …..

Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months

Moore’s Law Electronics, April 19, 1965.

Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 i386 100 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Courtesy, Intel

Moore’s law in Microprocessors 1000 2X growth in 1.96 years! 100 10 P6 Pentium® proc Transistors (MT) 1 486 386 0.1 286 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Transistors on Lead Microprocessors double every 2 years Courtesy, Intel

Die size grows by 14% to satisfy Moore’s Law Die Size Growth 100 P6 Pentium ® proc Die size (mm) 486 10 386 286 8080 8086 8085 ~7% growth per year 8008 ~2X growth in 10 years 4004 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

Die Cost Single die Wafer Going up to 12” (30cm) From http://www.amd.com

Lead Microprocessors frequency doubles every 2 years 10000 Doubles every 2 years 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 10 386 8085 8086 286 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel

Lead Microprocessors power continues to increase Power Dissipation 100 P6 Pentium ® proc 10 486 286 Power (Watts) 8086 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel

Power will be a major problem 100000 18KW 5KW 10000 1.5KW 1000 500W Pentium® proc Power (Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel

Power density too high to keep junctions at low temp 10000 Rocket Nozzle 1000 Nuclear Reactor Power Density (W/cm2) 100 8086 10 Hot Plate 4004 P6 8008 8085 386 Pentium® proc 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel

More information http://www.intel.com/technology/timeline.pdf http://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures http://en.wikipedia.org/wiki/Intel_Core

Not Only Microprocessors (cell phone…) Analog Baseband Digital Baseband (DSP + MCU) Power Management Small Signal RF RF

Challenges in Digital Design µ DSM (deep submicron) µ 1/DSM “Microscopic Problems” • Ultra-high speed design Interconnect • Noise, Crosstalk • Reliability, Manufacturability • Power Dissipation • Clock distribution. Everything Looks a Little Different “Macroscopic Issues” • Time-to-Market • Millions of Gates • High-Level Abstractions • Reuse & IP: Portability • Predictability • etc. …and There’s a Lot of Them! ?

Complexity outpaces design productivity Productivity Trends Logic Transistor per Chip (M) 10,000,000 10,000 1,000 100 10 1 0.1 0.01 0.001 100,000,000 0.01 0.1 1 10 100 1,000 10,000 100,000 Logic Tr./Chip 1,000,000 10,000,000 Tr./Staff Month. 100,000 1,000,000 Complexity 58%/Yr. compounded 10,000 (K) Trans./Staff - Mo. Productivity 100,000 Complexity growth rate 1,000 10,000 x x 100 1,000 x x 21%/Yr. compound x x x Productivity growth rate x 10 100 1 10 2003 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2005 2007 2009 Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap

Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstraction

Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S D n+ n+

Design Metrics How to evaluate performance of a digital integrated circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area

NRE Cost is Increasing

Die Cost Single die Wafer Going up to 12” (30cm) From http://www.amd.com

Cost per Transistor cost: ¢-per-transistor 1 Fabrication capital cost per transistor (Moore’s law) 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Yield

Defects a is approximately 3

Some Examples Chip Metal layers Line width Wafer cost Def./ cm2 Area mm2 Dies/wafer Yield Die cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486 DX2 3 0.80 $1200 81 181 54% $12 Power PC 601 4 $1700 1.3 121 115 28% $53 HP PA 7100 $1300 196 66 27% $73 DEC Alpha 0.70 $1500 1.2 234 53 19% $149 Super Sparc 1.6 256 48 13% $272 Pentium 1.5 296 40 9% $417

Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

Reliability― Noise in Digital Integrated Circuits v ( t ) V DD i ( t ) Inductive coupling Capacitive coupling Power and ground noise

The Ideal Inverter Gate out R i = ¥ R o = 0 Fanout = ¥ NMH = NML = VDD/2 g =  V in

DC Operation Voltage Transfer Characteristic V(x) V(y) V OH OL M f V(y)=V(x) Switching Threshold Nominal Voltage Levels VOH = f(VOL) VOL = f(VOH) VM = f(VM)

Mapping between analog and digital signals V IL IH in Slope = -1 OL OH out V “ 1 ” OH V IH Undefined Region V IL “ ” V OL

Definition of Noise Margins "1" V OH Noise margin high NM H V IH Undefined Region NM V L Noise margin low IL V OL "0" Gate Output Gate Input

Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources

Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric – the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;

Regenerative Property Non-Regenerative

Regenerative Property 1 2 3 4 5 6 A chain of inverters Simulated response

Fan-in and Fan-out N Fan-out N M Fan-in M

Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

An Old-time Inverter Vout (V) 5.0 NM 4.0 3.0 2.0 V NM 1.0 0.0 1.0 2.0 H 1.0 0.0 1.0 2.0 3.0 4.0 5.0 V (V) in

Delay Definitions

Ring Oscillator T = 2 ´ t p N This is actually a de-facto circuit for measuring the delay so that technologies can be compared on a equal basis

A First-Order RC Network v out in C R tp = ln (2) t = 0.69 RC Important model – matches delay of inverter

Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function

Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power: Ppeak = Vsupplyipeak Average power:

Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = Pav  tp Energy-Delay Product (EDP) = quality metric of gate = E  tp

A First-Order RC Network v out v in CL

Summary Digital integrated circuits have come a long way and still have quite some potential for the coming decades (also more challenges) Hierarchical design methodology and design automation tools are keys to cope with VLSI design complexity Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation