INEL 4207. Dynamic logic timing sequence Figure 14.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the.

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Presentation transcript:

INEL 4207

Dynamic logic timing sequence Figure (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.

Example Y=ABCD Fig a) Dynamic Logic Circuit Fig b)Precharge Phase,  =0 Fig c)Evaluation Phase,  =1

Example Problem Assume VDD = 1.8V : Vt = 0.5V μ n C ox = 4μ p C ox = 0.3mA/V 2 (W/L)n =0.27μm/0.18μm (including Qe), (W/L)p = 0.54μm/0.18μm (for Qp), C L =20fF. a) For the pre-charge operation, with Qp’s gate at 0V and if C L is fully discharged at t = 0, find the time for v Y to rise from 10% to 90% of VDD. b) For A = B = C = D = 1, find tPHL

Calculation of rise time Calculating rise time (t r ) the signal at the output goes from 10% its final value to 90% its final value. Final Value is V DD V Y =0.1V DD =0.18V; Q e is in Saturation mode For rise time we are at precharge

Calculation of rise time At V Y =0.9VDD=1.62V; Q P is in triode mode

Rise Time Average Current, I av =(i 1 +i 2 )/2 I av =119.6uA

Propagation delay High to Low  When A=B=C=D=1, All Ntransistors are on.  Replace 5 identical transistor with 1 equivalent trans.  Q eq has a W/L=1/5(W/L)=0.3 For V Y =V DD Q eq in sat.

At VY=VDD/2; Qeq is in triode region  Iav=72.5 uA Propagation delay High to Low

Cascading dynamic logic gates Figure Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase CL2 will partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction. By the time vY1 drops to Vt, CL2 can loose a significant amount of charge causing vY2 to can be significantly reduced.

A cascadable Dynamic Logic gate Domino Logic

Figure The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0- to-1 transition (to VDD).

Cascaded Domino Logic Gate End of Precharge X1=VDD Y1=0; X2=VDD and Y2=0 If A=1 as f goes high CL1 will start discharge through Q1but Q2 will remain off (CL2 charged) until x1 falls below the vtn of the inverter I1, Y1 goes up Q2 will turn on and then CL2 will discharge., not before)