Lecture 17: Adders.

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Presentation transcript:

Lecture 17: Adders

Outline Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder 17: Adders

Single-Bit Addition Half Adder Full Adder A B Cout S 1 A B C Cout S 1 1 A B C Cout S 1 17: Adders

PGK For a full adder, define what happens to carries (in terms of A and B) Generate: Cout = 1 independent of C G = A • B Propagate: Cout = C P = A  B Kill: Cout = 0 independent of C K = ~A • ~B 17: Adders

Full Adder Design I Brute force implementation from eqns 17: Adders

Full Adder Design II Factor S in terms of Cout S = ABC + (A + B + C)(~Cout) Critical path is usually C to Cout in ripple adder 17: Adders

Layout Clever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters 17: Adders

Full Adder Design III Complementary Pass Transistor Logic (CPL) Slightly faster, but more area 17: Adders

Full Adder Design IV Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers 17: Adders

Carry Propagate Adders N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickly? 17: Adders

Carry-Ripple Adder Simplest design: cascade full adders Critical path goes from Cin to Cout Design full adder to have fast carry delay 17: Adders

Inversions Critical path passes through majority gate Built from minority + inverter Eliminate inverter and use inverting full adder 17: Adders

Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Base case Sum: 17: Adders

PG Logic 17: Adders

Carry-Ripple Revisited 17: Adders

Carry-Ripple PG Diagram 17: Adders

PG Diagram Notation 17: Adders

Carry-Skip Adder Carry-ripple is slow through all N stages Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal 17: Adders

Carry-Skip PG Diagram For k n-bit groups (N = nk) 17: Adders

Variable Group Size Delay grows as O(sqrt(N)) 17: Adders

Carry-Lookahead Adder Carry-lookahead adder computes Gi:0 for many bits in parallel. Uses higher-valency cells with more than two inputs. 17: Adders

CLA PG Diagram 17: Adders

Higher-Valency Cells 17: Adders

Carry-Select Adder Trick for critical paths dependent on late input X Precompute two possible outputs for X = 0, 1 Select proper output when X arrives Carry-select adder precomputes n-bit sums For both possible carries into n-bit group 17: Adders

Carry-Increment Adder Factor initial PG and final XOR out of carry-select 17: Adders

Variable Group Size Also buffer noncritical signals 17: Adders

Tree Adder If lookahead is good, lookahead across lookahead! Recursive lookahead gives O(log N) delay Many variations on tree adders 17: Adders

Brent-Kung 17: Adders

Sklansky 17: Adders

Kogge-Stone 17: Adders

Tree Adder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels: L + l Fanout: 2f + 1 Wiring tracks: 2t Known tree adders sit on plane defined by l + f + t = L-1 17: Adders

Tree Adder Taxonomy 17: Adders

Han-Carlson 17: Adders

Knowles [2, 1, 1, 1] 17: Adders

Ladner-Fischer 17: Adders

Taxonomy Revisited 17: Adders

Summary Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application. Architecture Classification Logic Levels Max Fanout Tracks Cells Carry-Ripple N-1 1 N Carry-Skip n=4 N/4 + 5 2 1.25N Carry-Inc. n=4 N/4 + 2 4 2N Brent-Kung (L-1, 0, 0) 2log2N – 1 Sklansky (0, L-1, 0) log2N N/2 + 1 0.5 Nlog2N Kogge-Stone (0, 0, L-1) N/2 Nlog2N 17: Adders