ACOE301 – Computer Architecture II

ACOE301 - Computer Architecture II - Frederick University Useful Information Instructor: Lecturer K. Tatas Office hours : Mo5, Tu3, We6-8, Fri5 E-mail: com.tk@fit.ac.cy http://staff.fit.ac.cy/com.tk Prerequisites: ACOE201 Lectures/week: 3 + 1 (Lab) ECTS: 5 (x25 h) = 125h Evaluation: 60% Final exam – 20% Labs/Quizzes – 20% midterm/assignment Enrollment key: ACOE301_FALL12 ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Course Objectives Introduce students to computer architecture and organization with emphasis on performance metrics and cost, instruction set architectures, RISC processor design, Pipelining memory hierarchy. ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Course Outcomes By the end of this course students should be able to: Understand the computer architecture and organization of modern processors. Further advance their knowledge in designing computer architecture systems using Assembly, C/C++ and VHDL. ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Course Description Introduction to Computer Architecture: Organisation and abstraction of a computer. ISAs. Emerging computer architecture technologies. Processor, caches, memory and  I/O devices. Instruction Set Architecture (ISA): Specifications, classes, registers, memory addressing and addressing modes. The complete MIPS architecture and in-depth analysis. ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Course Description RISC Processor Design: Full ALU design of the MIPS processor. Multiplication and division algorithms in hardware. Single-cycle, multi-cycle datapath and controller design. Performance Metrics: Measuring performance and metrics. Improve performance, clock cycles, CPI, instructions count, MIPS, MOPS, MFLOPs. Benchmarks. Amdahl's Law. ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Course Description Pipelining: Single-cycle, Multi-cycle versus Pipeline. Structural, data and control hazards. Forwarding. Exceptions. MIPS R3000 pipeline and design of a pipelined processor. Loop unrolling in scalar and superscalar computer systems. Software pipelining. Memory Hierarchy: Locality and memory hierarchy. SRAM and DRAM. Memory organization. Advanced cache memory. Virtual memory. Protection. Translation Lookaside Buffer (TLB). ACOE301 - Computer Architecture II - Frederick University

Textbook and References Paterson, Hennessy, Computer Organisation and Design: the Hardware/Software Interface, Morgan Kaufman, 2003. M. Mano, C. R. Kime, Logic and Computer Design Fundamentals, Prentice Hall, 2004 J. P. Hayes, Computer Architecture and Organization, 3Ed, McGraw Hill., 1998 ACOE301 - Computer Architecture II - Frederick University

The task of the computer designer Determine what attributes are important for a new machine, then design a machine to maximize performance while staying within cost and power constraints. This task has many aspects instruction set design functional organization logic design implementation. integrated circuit design Packaging Power cooling Optimizing the design requires familiarity with a very wide range of technologies: Compilers operating systems packaging. ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Basic Terminology instruction set architecture refers to is the part of the processor that is visible to the programmer or compiler writer. The instruction set architecture serves as the boundary between the software and hardware Hardware is used to refer to the specifics of a machine detailed logic design Implementation/packaging technology Often a line of machines contains machines with identical instruction set architectures and nearly identical organizations, but they differ in the detailed hardware implementation. For example, the Pentium II and Celeron are nearly identical, but offer different clock rates and different memory systems, In this course the word computer architecture is intended to cover all three aspects of computer design instruction set architecture Organization hardware ACOE301 - Computer Architecture II - Frederick University

HISTORICAL PERSPECTIVE 1st generation: 1945 - 1955 Tubes, punchcards 2nd generation: 1955 - 1965 transistors 3rd generation: 1965 – 1980 Integrated circuits 4th generation: 1980 – PCs and workstations ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University 1st generation (1945-1955) Programming was done in machine language No operating system Programming and maintenance done by one group of people ACOE301 - Computer Architecture II - Frederick University

ENIAC – The first electronic computer (1946) 18,000 tubes 300 Tn 170 KWatt ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University 2nd generation (1955-1965) Transistor-based Fairly reliable Clear distinction between designers, manufacturers, users, programmers, and support personnel. Only afforded by governments, universities or large companies (millions $) ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University 2nd generation (1955-1965) Program was first written on paper (FORTRAN) and then punched into cards Cards were then delivered to the user. Mostly used for scientific and technical calculations Solving differential equations ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University 3rd generation (1965-1980) IC-based operation IBM develops compatible systems Tradeoffs in performance, memory, I/O etc). Greater MHz/$ ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University 4th generation (1980-1990) LSI-based PCs Significantly cheaper User-friendly software 2 dominant operating systems: MS DOS: IBM PC (8088, 80286, 80386, 80486) UNIX: RISC workstations ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University 5th generation (1990-) PC networks Network operating systems Each machine runs its own operating system Users don’t care where their programs are being executed ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Famous quotes “Future computers may weigh less than 1,5 tn”, (1949) “I believe there is a world market for five computers”, T. Watson, IBM CEO (1943) “There is no particular reason why someone would want a computer at home”, K. Oslon, president of DEC (1974) “640Κbytes of memory should be enough for anybody”, B. Gates, president of Microsoft (1981) ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

Microprocessor Technologies (Orthogonal) VLSI technology Computer Architecture Compiler technology ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Moore’s Law ACOE301 - Computer Architecture II - Frederick University

Intel 4004 Micro-Processor ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Recent advances ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University The Future: 3D ICs Memory Processor RF Chip DNA Chip MEMS Battery Image Sensor 3D integration: One chip ACOE301 - Computer Architecture II - Frederick University

Computer Architecture ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University RISC vs. CISC Complex instruction set computer (CISC): Large instruction set; Complex operations; Complex addressing modes; Complex hardware, long execution time; Minimum number of instructions needed for a given task; Easy to program, simpler compiler. Reduced instruction set computer (RISC): Small instruction set; Simple instructions to allow for fast execution (fewer steps); Large number of registers; Only read/write (load/store) instructions should access the main memory, one MM access per instruction; Simple addressing modes to allow for fast address computation; Fixed-length instructions with few formats and aligned fields to allow for fast instruction decoding; increased compiler complexity and compiling time; simpler and faster hardware implementation, pipelined architecture. ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University RISC vs. CISC example CISC (M68000) Add the content of MM location pointed to by A3 to the component of an array starting at MM address 100. The index number of the component is in A2. The content of A3 is then automatically incremented by 1. RISC (MIPS) ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Memory Architecture Von Neumann: Common memory for data and instructions Harvard: Separate data and instruction memories ACOE301 - Computer Architecture II - Frederick University

Von Neumann Memory Architecture address CPU PC 200 data 200 ADD r5,r1,r3 ADD r5,r1,r3 IR ACOE301 - Computer Architecture II - Frederick University

Harvard Memory Architecture address CPU data memory data PC address program memory data ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University Pipelining Dividing the processing task into stages, which are executed in parallel ACOE301 - Computer Architecture II - Frederick University

Application-Specific Processors Processors optimized for a specific application domain DSP processors Multiplier/accumulator in ALU, Harvard memory architecture Multimedia processors Image processing/video hardware accelerators ACOE301 - Computer Architecture II - Frederick University

Assembler/Compiler technologies Increased productivity by using high-level languages For critical tasks and embedded systems, assembly is commonly used ACOE301 - Computer Architecture II - Frederick University

ACOE301 - Computer Architecture II - Frederick University References Weste, Harris, CMOS VLSI Design: A Circuits and Systems Perspective Patterson, Hennessy - Computer Organization and Design; The Hardware-Software Interface, 2E (Morgan Kaufman, 1997) Fundamentals Of Computer Organization And Architecture (2005) Wiley ACOE301 - Computer Architecture II - Frederick University