Status and plans for LHC DC BCT systems P.Odier DC BCT hardware modifications Proposal for choice of acquisition system (VD80 or 24- bit ADC) for the CCC M.Ludwig Software status and plans including intensity transmission P.Odier BI-TB

Hardware modifications (1) P.Odier BI-TB Installation around the ceramic gap of a pair of additional toroidal magnetic cores per DC Beam Current Transformers. Potential improvement of the RF bypass efficiency. Designed by N.Jurado RF bypassBunch spacing [ns] Limit of the DCCT bunch charge Without additional cores 502.8E E11 With additional cores 50Tested up to 3.8E11 (limit of the bench test) 25Tested up to 1.9E11 (limit of the bench test) ECR: Toroidal Magnetic Cores Installation in the LHC Beam Current Transformers System The cores may be either inserted or not in the bypass circuit. Not foreseen in 2015 but ready for higher batch intensity (higher bunch density and shorter bunch spacing). Limit before LS2≈1.3E11 ppb with 25ns (according to J.Wenniger)

Hardware modifications (2) P.Odier BI-TB Acquisition system New 16 bit ADC (VD80) to replace the old 12 bit (MPV908) New CPU (Linux), FESA 3 (see Michael’s presentation) Test of a new VME module to receive and synchronise the 24 bit data stream acquired with the ADC located next to the monitor Before LS1: VME RF MUX (D.Belohrad) no longer considered as standard + Mezzanine (S.Thoulet) After LS1: Plan to install 1 VFC-HPC (A.Boccardi) the new BI standard ! + new Mezzanine (S.Thoulet) on BCTDCs B (ring 1 and 2)

Acquisition system before LS1 P.Odier BI-TB

Acquisition system after LS1 P.Odier BI-TB

Detail of the acquisition system P.Odier BI-TB

Acquisition systems, summary P.Odier BI-TB Acquisition system Current statusExpected status in March 2015 Proposal for the CCC in 2015 Plan for 2016 VD80 (16 bit) NEW Needs SW modification (M.Ludwig) Operational for all BCTDCs SpareSpare + auxiliary signals 24 bit on VME-RF- MUX Tested (L.Jensen) Operational for the BCTDCs 1A and 2A in crate 3 Main systemCrate 3 dismantled 24 bit on VFC-HPC NEW Firmware under development in the laboratory (S.Thoulet, A.Boccardi). SW to be implemented (L.Jensen) Under test for the BCTDCs 1B and 2B in crate 3 TestingInstalled in crates A and B. Main system

SW for the DCCT FEC: Class Fesa3::BCTDCLHC2, A and B system, including arbiter flag, middle-tier, workstation P.Odier BI-TB Functional itemStatus and comment Basic acquisition, including expert debugging Verification in progress. VD80 morphing into mpv908 structure. Select ADC Quick calibration sequenceFailed (VD80), repeat again Precision calibration, choice of calibration set Not yet tested Intensity transmission for telegram, SBF, through optical link & MTT BI MTT end seems OK, but overall chain not working: LHC-OP and MP (Puccio), Tests SBF documented in EDMS# for MP Post MortemNot yet implemented, format unchanged, but compatibility issues expected Lifetime API “30sec rolling buffer”Not yet implemented, format unchanged, no further issues expected DeployRely on fesa3 support

SW for the DCCT Middle tier: Class Fesa??::LIFETIME P.Odier BI-TB Functional itemStatus and comment Acquire lifetime API from BCTDCLHC2 Verification in progress. VD80 morphing into mpv908 structure. Select ADC Fast ring BCT ?API for lifetime not decided Analyze dI/dt seconds-minutesReactivity precision, much SW tweaking Provide lifetime: JJG algorithm, AB algorithm Lots of constraints imposed, time consuming, complex DeployRely on fesa3 support

SW for the DCCT Workstation tools P.Odier BI-TB Functional itemStatus and comment Expert low level debuggingData collection for statistics is available Expert GUIWill implement in C++/Qt It will be impossible to have all this fully working in time for LHC startup 03/2015. There are many reasons for delays… Clarify “operational systems”: is the A and really needed ? This is a lot of work for a temporary system Objective: have basic FEC SW up & running Tools and modules (lifetime, PM..) come later during 2015