ECE 331 – Digital System Design Counters (Lecture #18)

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Presentation transcript:

ECE 331 – Digital System Design Counters (Lecture #18)

ECE Digital System Design2 3-bit Counter: State Diagram

ECE Digital System Design3 Asynchronous Counters (aka. Ripple Counters) Counters

ECE Digital System Design4 3-bit (up) Counter Let each bit in the counter be represented by the output of a flip-flop. CountQ2Q2 Q1Q1 Q0Q

ECE Digital System Design5 3-bit (up) Counter: T Flip-Flops T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 Q 0 Q 1 Q 2 Count Asynchronous Counter Counter does not use a common clock.

ECE Digital System Design6 Synchronous Counters Counters

ECE Digital System Design7 4-bit (up) Counter As before, let each bit in the counter be represented by the output of a flip-flop. CountQ3Q3 Q2Q2 Q1Q1 Q0Q Q3Q3 Q2Q2 Q1Q1 Q0Q

ECE Digital System Design8 4-bit (up) Counter: T Flip-Flops

ECE Digital System Design9 4-bit (up) Counter: JK Flip-Flops Synchronous Counter Counter uses a common clock.

ECE Digital System Design10 4-bit Counter: D Flip-Flops Clock Enable D Q Q D Q Q D Q Q D Q Q Q 0 Q 1 Q 2 Q 3 Output carry How does the XOR gate function when the Enable signal is a logic-1?

ECE Digital System Design11 Synchronous Counters 4-bit (up) Counter with Enable and Clear

ECE Digital System Design12 T Q Q Clock T Q Q Enable Clear T Q Q T Q Q 4-bit Counter with Enable and Clear asynchronous control signals

ECE Digital System Design13 Synchronous Counters 4-bit (up) Counter with Parallel Load

ECE Digital System Design14 4-bit Counter with Parallel Load Is the Load signal active-high or active-low?

ECE Digital System Design15 4-bit Counter with Parallel Load

ECE Digital System Design16 Synchronous Counters Modulo-6 Counter

ECE Digital System Design17 Modulo-6 Counter: D Flip-Flops Clock Count Q 0 Q 1 Q 2 Enable Q 0 Q 1 Q 2 D 0 D 1 D 2 Load Clock bit counter with Parallel Load Counter resets to zero when count reaches six.

ECE Digital System Design18 Modulo-6 Counter: T Flip-Flops T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 Q 0 Q 1 Q 2 Count asynchronous clear signal Counter cleared when count reaches six.

ECE Digital System Design19 Counters BCD (Decimal) Counter (aka. Modulo-10 Counter)

ECE Digital System Design20 BCD Counter: State Diagram

ECE Digital System Design21 BCD Counter: JK Flip-Flops Asynchronous Counter

ECE Digital System Design22 BCD Counter: D Flip-Flops Synchronous Counter

ECE Digital System Design23 Up / Down Counter Synchronous Counters

ECE Digital System Design24 4-bit Up / Down Counter

ECE Digital System Design25 Acknowledgments The slides used in this lecture were taken, with permission, from those provided by McGraw-Hill for Fundamentals of Digital Logic with VHDL Design (3 rd Edition). They are the property of and are copyrighted by McGraw-Hill Higher Education.