Dale & Lewis Chapter 5 Computing components
Let’s design a computer Generic CPU with registers −Program counter (PC) – 5 bits (size of addresses) −Instruction register (IR) – 8 bits (op code + address) −Memory Address Register (MAR) – 5 bits Main Memory −Memory Data Register (MDR) – 8 bits (byte addressable) −Accumulator (A or Acc) – 8 bits
Instructions Instruction format: 3-bit op code, 5-bit address Instructions and their op codes op codeInstruction 000 HALT (HLT) 001 LOAD (LDA) 010 STORE (STA) 011 ADD (ADD) 100 SUBTRACT (SUB) 101 BRANCH (BR) 110 BRANCH ON ZERO (BRZ) 111 BRANCH ON POSITIVE (BRP)
Types of instructions Data movement −Move data between memory and CPU −Move data between different memory locations −Input, output Arithmetic and logic operations −Integer arithmetic −Comparing two quantities −Shifting or rotating bits in a quantity −Testing, comparing and converting bits Program control −Starting a program −Halting a program −Skipping to another location −Testing data to decide whether to skip to another instruction
Instructions LOAD instruction (LDA) −PC MAR −MDR IR −IR [address] MAR −MDR A −PC + 1 PC ADD instruction (ADD) −PC MAR −MDR IR −IR [address] MAR −A + MDR A −PC + 1 PC STORE instruction (STA) −PC MAR −MDR IR −A MDR −IR [address] MAR −PC + 1 PC HALT instruction (HLT) −PC MAR −MDR IR −stop FETCH – DECODE – GET DATA – EXECUTE
FETCH Address of next instruction is transferred from PC to MAR and the instruction is located in the memory
FETCH Instruction is copied from memory to the MDR
DECODE Decode the instruction
EXECUTE Execute the instruction – control unit sends signals to appropriate devices to carry out execution of the instruction
A small computer program LOADA ADDB STOREC HLT ADATA BDATA CDATA Program Assembly language Main memory Address Contents op code Data
etc… AddressContents PC IR Acc MAR MDR CPU
etc… AddressContents PC IR Acc MAR MDR CPU The program starts
etc… AddressContents PC IR Acc MAR MDR CPU Fetch 1 st instruction
etc… AddressContents PC IR Acc MAR MDR CPU Decode 1 st instruction: LOAD A
etc… AddressContents PC IR Acc MAR MDR CPU Execute1 st instruction: LOAD A
etc… AddressContents PC IR Acc MAR MDR CPU Advance PC
etc… AddressContents PC IR Acc MAR MDR CPU Fetch 2 nd instruction
etc… AddressContents PC IR Acc MAR MDR CPU Decode 2 nd instruction: ADD B
etc… AddressContents PC IR Acc MAR MDR CPU Execute 2 nd instruction: ADD B
etc… AddressContents PC IR Acc MAR MDR CPU Advance PC, etc…