Synthesis of Loop-free Programs Sumit Gulwani (MSR), Susmit Jha (UC Berkeley), Ashish Tiwari (SRI) and Ramarathnam Venkatesan(MSR) Susmit Jha 1.

Slides:



Advertisements
Similar presentations
Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Introduction An overview of formal methods for hardware.
Advertisements

Models of Computation Prepared by John Reif, Ph.D. Distinguished Professor of Computer Science Duke University Analysis of Algorithms Week 1, Lecture 2.
50.530: Software Engineering
Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Masahiro Fujita Yoshihisa Kojima University of Tokyo May 2, 2008
CS 267: Automated Verification Lecture 8: Automata Theoretic Model Checking Instructor: Tevfik Bultan.
A System to Generate Test Data and Symbolically Execute Programs Lori A. Clarke September 1976.
Satisfiability Modulo Theories (An introduction)
SMT Solvers (an extension of SAT) Kenneth Roe. Slide thanks to C. Barrett & S. A. Seshia, ICCAD 2009 Tutorial 2 Boolean Satisfiability (SAT) ⋁ ⋀ ¬ ⋁ ⋀
Promising Directions in Hardware Design Verification Shaz Qadeer Serdar Tasiran Compaq Systems Research Center.
Synthesizing Geometry Constructions Sumit Gulwani MSR, Redmond Vijay Korthikanti UIUC Ashish Tiwari SRI.
Verification of Evolving Software Natasha Sharygina Joint work with Sagar Chaki and Nishant Sinha Carnegie Mellon University.
ECE Synthesis & Verification - L271 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Model Checking basics.
Programming with Constraint Solvers CS294: Program Synthesis for Everyone Ras Bodik Emina Torlak Division of Computer Science University of California,
Sumit Gulwani Microsoft Research, Redmond Dimensions in Program Synthesis ACM Symposium on Principles and Practice of Declarative.
Timed Automata.
Efficient Reachability Analysis for Verification of Asynchronous Systems Nishant Sinha.
Program Analysis as Constraint Solving Sumit Gulwani (MSR Redmond) Ramarathnam Venkatesan (MSR Redmond) Saurabh Srivastava (Univ. of Maryland) TexPoint.
SAT and Model Checking. Bounded Model Checking (BMC) A.I. Planning problems: can we reach a desired state in k steps? Verification of safety properties:
Department of Electrical and Computer Engineering M.A. Basith, T. Ahmad, A. Rossi *, M. Ciesielski ECE Dept. Univ. Massachusetts, Amherst * Univ. Bretagne.
1 Predicate Abstraction of ANSI-C Programs using SAT Edmund Clarke Daniel Kroening Natalia Sharygina Karen Yorav (modified by Zaher Andraus for presentation.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
TexPoint fonts used in EMF. Read the TexPoint manual before you delete this box.: A A Sumit Gulwani (MSR Redmond) Component-based Synthesis Susmit Jha.
Bounded Model Checking EECS 290A Sequential Logic Synthesis and Verification.
Validating High-Level Synthesis Sudipta Kundu, Sorin Lerner, Rajesh Gupta Department of Computer Science and Engineering, University of California, San.
Usable Synthesis Sumit Gulwani Microsoft Research, Redmond Usable Verification Workshop November 2010 MSR Redmond.
Synthesis of Interface Specifications for Java Classes Rajeev Alur University of Pennsylvania Joint work with P. Cerny, G. Gupta, P. Madhusudan, W. Nam,
Semantics with Applications Mooly Sagiv Schrirber html:// Textbooks:Winskel The.
The Superdiversifier: Peephole Individualization for Software Protection Mariusz H. Jakubowski Prasad Naldurg Chit Wei (Nick) Saw Ramarathnam Venkatesan.
Computing Over­Approximations with Bounded Model Checking Daniel Kroening ETH Zürich.
Program Synthesis for Automating Education Sumit Gulwani Microsoft Research, Redmond.
1 Formal Engineering of Reliable Software LASER 2004 school Tutorial, Lecture1 Natasha Sharygina Carnegie Mellon University.
Formal Verification of SpecC Programs using Predicate Abstraction Himanshu Jain Daniel Kroening Edmund Clarke Carnegie Mellon University.
Farzan Fallah Srinivas Devadas Laboratory for Computer Science MIT Farzan Fallah Srinivas Devadas Laboratory for Computer Science MIT Functional Vector.
Daniel Kroening and Ofer Strichman Decision Procedure
272: Software Engineering Fall 2012 Instructor: Tevfik Bultan Lecture 4: SMT-based Bounded Model Checking of Concurrent Software.
Dimensions in Synthesis Sumit Gulwani Microsoft Research, Redmond May 2012.
An SMT Based Method for Optimizing Arithmetic Computations in Embedded Software Code Presented by: Kuldeep S. Meel Adapted from slides by Hassan Eldib.
Relational Verification to SIMD Loop Synthesis Mark Marron – IMDEA & Microsoft Research Sumit Gulwani – Microsoft Research Gilles Barthe, Juan M. Crespo,
272: Software Engineering Fall 2012 Instructor: Tevfik Bultan Lecture 17: Code Mining.
Smten: Automatic Translation of High-level Symbolic Computations into SMT Queries Richard Uhler (MIT-CSAIL) and Nirav Dave (SRI International) CAV 2013.
Generative Programming Meets Constraint Based Synthesis Armando Solar-Lezama.
Dimensions in Synthesis Part 3: Ambiguity (Synthesis from Examples & Keywords) Sumit Gulwani Microsoft Research, Redmond May 2012.
Analysis of Algorithms
CS6133 Software Specification and Verification
Predicate Abstraction of ANSI-C Programs Using SAT By Edmund Clarke, Daniel Kroening, Natalia Sharygina, Karen Yorav Presented by Yunho Kim Provable Software.
CSCI 3160 Design and Analysis of Algorithms Tutorial 10 Chengyu Lin.
Chapter 2: General Problem Solving Concepts
1 Incorporating Iterative Refinement with Sparse Cholesky April 2007 Doron Pearl.
Architectural Point Mapping for Design Traceability Naoyasu Ubayashi and Yasutaka Kamei Kyushu University, Japan March 26, 2012 FOAL 2012 (AOSD Workshop)
Programming at a high level. Developing a Computer Program Programmer  Writes program in source code (VB or other language) Compiler  Converts source.
On the Relation between SAT and BDDs for Equivalence Checking Sherief Reda Rolf Drechsler Alex Orailoglu Computer Science & Engineering Dept. University.
CS703: PROJECT GUIDELINES 1. Logistics: Project Most important part of the course Teams of 1 or 2 people Expectations commensurate with size of team Deliverables.
Symbolic and Concolic Execution of Programs Information Security, CS 526 Omar Chowdhury 10/7/2015Information Security, CS 5261.
Theory-Aided Model Checking of Concurrent Transition Systems Guy Katz, Clark Barrett, David Harel New York University Weizmann Institute of Science.
Superoptimization Venkatesh Karthik Srinivasan Guest Lecture in CS 701, Nov. 10, 2015.
From Verification to Synthesis Sumit Gulwani Microsoft Research, Redmond August 2013 Marktoberdorf Summer School Lectures: Part 1.
Bounded Model Checking A. Biere, A. Cimatti, E. Clarke, Y. Zhu, Symbolic Model Checking without BDDs, TACAS’99 Presented by Daniel Choi Provable Software.
Verifying Component Substitutability Nishant Sinha Sagar Chaki Edmund Clarke Natasha Sharygina Carnegie Mellon University.
1 Computing Abstractions by integrating BDDs and SMT Solvers Alessandro Cimatti Fondazione Bruno Kessler, Trento, Italy Joint work with R. Cavada, A. Franzen,
© Anvesh Komuravelli Spacer Model Checking with Proofs and Counterexamples Anvesh Komuravelli Carnegie Mellon University Joint work with Arie Gurfinkel,
On the Relation Between Simulation-based and SAT-based Diagnosis CMPE 58Q Giray Kömürcü Boğaziçi University.
SS 2017 Software Verification Bounded Model Checking, Outlook
Susmit Jha1, Vasumathi Raman, Sanjit A. Seshia2 1SRI International
Complete Program Synthesis for Linear Arithmetics
Canonical Computation without Canonical Data Structure
Templates of slides for P4 Experiments with your synthesizer
CSC-682 Advanced Computer Security
Canonical Computation without Canonical Data Structure
Predicate Abstraction
Presentation transcript:

Synthesis of Loop-free Programs Sumit Gulwani (MSR), Susmit Jha (UC Berkeley), Ashish Tiwari (SRI) and Ramarathnam Venkatesan(MSR) Susmit Jha 1

From Verification to Synthesis Automated synthesis of systems is the holy grail of computer science and engineering. Back to the future “ We propose a method of constructing concurrent programs in which the synchronization skeleton of the program is automatically synthesized from a high-level (branching time) Temporal Logic specification.” - Edmund M. Clarke, E. Allen Emerson ‘Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic’ Logic of Programs 1981: Susmit Jha 2

From Verification to Synthesis Many formal verification techniques exploit the advancements in constraint solving: SAT, SMT Can we extend verification techniques for automated synthesis. Synthesis as an aid to designers and developers Focus on tedious and non-intuitive parts of programs which are hard-to-get right by humans and more amenable to automated search based on constraint solvers. Susmit Jha 3

Motivating Example 1: Floor of two integers’ average Susmit Jha 4

Motivating Example 1: Floor of two integers’ average Susmit Jha 5

Motivating Example 1: Floor of two integers’ average Susmit Jha 6

Motivating Example 2: Bit twiddling programs Turn off rightmost contiguous 1 bits   TurnoffRmOnes (x) { i = length(x) – 1; while( x[i] == 0 ){ i--; if (i < 0) return x; } x[i] = 0; i--; while( x[i] == 1 ){ x[i] = 0; i--; if (i < 0) return x; } return x; } Arithmetic: add, subtract, etc Logical: bitwise-or, bitwise-and, bitwise-xor, left-shift, etc. Performance critical Non-intuitive to write Susmit Jha 7

Motivating Example 2: Bit twiddling programs Turn off rightmost contiguous 1 bits   TurnoffRmOnes (x) { i = length(x) – 1; while( x[i] == 0 ){ i--; if (i < 0) return x; } x[i] = 0; i--; while( x[i] == 1 ){ x[i] = 0; i--; if (i < 0) return x; } return x; } Susmit Jha 8 TurnoffRmOnes (x) { r 1 = x – 1; r 2 = x || r 1 ; r 3 = r 2 + 1; r 4 = r 3 && x return r 4 ; }

Given: Library of components with their functional specification Logical Specification of desired behavior Inefficient programs Logical formula over input and output Obtain: Loop-free Programs using given components with desired behavior. Problem Definition Susmit Jha 9

In rest of the talk Encoding Program Space Symbolically Counter-example Guided Search for Correct Program Correctness Guarantees Experimental Results Conclusion Susmit Jha 10

Back to Example Turn off rightmost contiguous 1 bits Component Library - 1 || +1 && ! p1p1 p2p2 p3p3 p4p4 p5p5 p6p6 p7p7 r1r1 r2r2 r3r3 r4r4 r5r5 Components for correct program Extra Components Discover composition of these components that satisfies given specification Susmit Jha 11

Component Composition - 1 || SomethingElse (x) { r 1 = x – 1; r 5 = !x r 2 = r 5 || r 1 ; r 4 = r 2 && r 5 ; return r 4 ; } +1 && ! p1p1 p2p2 p3p3 p4p4 p5p5 p6p6 p7p7 r1r1 r2r2 r3r3 r4r4 r5r5 X o Each program form corresponds to some composition topology. Susmit Jha 12

Component Composition - 1 || Wrong (x) { r 1 = x – 1; r 2 = x || r 3 ; r 3 = r 2 + 1; r 4 = r 3 && x return r 4 ; } +1 && ! p1p1 p2p2 p3p3 p4p4 p5p5 p6p6 p7p7 r1r1 r2r2 r3r3 r4r4 r5r5 X o Some composition topology do not represent a valid program. UNDEFINED VAR ERROR ! Susmit Jha 13

Component Composition Program Synthesis Reduces to Searching Over Valid Composition of Library Components Encoding Valid Compositions into a logical formula Searching over this using satisfiability solving. Susmit Jha 14

Component Composition Susmit Jha 15

Component Composition Susmit Jha 16

Component Composition Susmit Jha 17

Component Composition Susmit Jha 18

Component Composition Susmit Jha 19

Component Composition Susmit Jha 20

Approach Space of all possible programs. Each dot represents a program corresponding to some value of L Susmit Jha 21

Approach Space of all possible programs Example I/O set E := {( I 1,O 1 )} such that Susmit Jha 22 Synthesis Constraint over E

Approach Space of all possible programs Example I/O set E := {( I 1,O 1 )} Susmit Jha 23 Verification Constraint on

Approach Space of all possible programs Example I/O set E := {( I 1,O 1 ),( I 2,O 2 )} such that Susmit Jha 24

Approach Space of all possible programs Example I/O set E := {( I 1,O 1 ),( I 2,O 2 )} Susmit Jha 25

Approach Space of all possible programs Example I/O set E := {( I 1,O 1 ),( I 2,O 2 ),…} Susmit Jha 26 Every verification call either finds one example which eliminates atleast one wrong program or reports that no such example exists in which case we report it as correct program.

Correctness Library of components is sufficient ? Correct design YES Infeasibility reported Set of minimal I,O examples NO Susmit Jha 27

28 Examples of Bitvector Algorithms P25: Higher order half of product of x and y o1 := and(x,0xFFFF); o2 : = shr(x,16); o3 := and(y,0xFFFF); o4 := shr(y,16); o5 := mul(o1,o3); o6 := mul(o2,o3); o7 := mul(o1,o4); o8 := mul(o2,o4); o9 := shr(o5,16); o10 := add(o6,o9); o11 := and(o10,0xFFFF); o12 := shr(o10,16); o13 := add(o7,o11); o14 := shr(o13,16); o15 := add(o14,o12); res := add(o15,o8); P24: Round up to next highest power of 2 o1 := sub(x,1); o2 := shr(o1,1); o3 := or(o1,o2); o4 := shr(o3,2); o5 := or(o3,o4); o6 := shr(o5,4); o7 := or(o5,o6); o8 := shr(o7,8); o9 := or(o7,o8); o10 := shr(o9,16); o11 := or(o9,o10); res := add(o10,1);

Runtime and Iterations: 29 ProgramBrahma Namelinesiterstime P1223 P2233 P3231 P4223 P5232 P6222 P7321 P8321 P9326 P P P ProgramBrahma Namelinesiterstime P13446 P P P P P P P P P P P P

Result Highlights Synthesized over 35 bit-manipulation programs from Hacker’s delight – Bible of bit-manipulation. Efficient Polynomial Evaluation Computing powers of a number efficiently. Program length: 2-16 Number of input/output examples: 2 to 15. Total runtime: < 1 second to 50 minutes. Susmit Jha 30

Some Related Work Bansal et al. Automatic Generation of Peephole Superoptimizers ASPLOS 06 Enumerates short sequences of instructions followed by fingerprint based testing and SAT based equivalence checking Solar-Lezama et al. Combinatorial sketching for finite programs. ASPLOS 06 2QBF Boolean satisfiability problem solved using counter- examples generated by equivalence checking Jha et al. Oracle-guided component-based program synthesis. ICSE 10 Specification is an input/output blackbox Susmit Jha 31

Limitations Library Size ? What to put in the library ? Runtime Number of Components Type of components: ITE, Multiplication are `hard’. Susmit Jha 32

Thanks ! Comments and Questions ? Susmit Jha 33 Synthesis of Loop-free Programs Sumit Gulwani (MSR), Susmit Jha (UC Berkeley), Ashish Tiwari (SRI) and Ramarathnam Venkatesan(MSR)

Motivating Example 3: Powers of a number - x^31 Susmit Jha 34

Susmit Jha 35

Motivation: Susmit Jha 36 public static int binarySearch(int[] a, int key) { int low = 0; int high = a.length - 1; while (low key) high = mid - 1; else return mid; // key found } return -(low + 1); // key not found. } From Google Research Blog: “The version of binary search that I wrote for the JDK contained the same bug. It was reported to Sun recently when it broke someone's program, after lying in wait for nine years or so. - Joshua Bloch”

Motivation: Susmit Jha 37 public static int binarySearch(int[] a, int key) { int low = 0; int high = a.length - 1; while (low key) high = mid - 1; else return mid; // key found } return -(low + 1); // key not found. } From Google Research Blog: “The version of binary search that I wrote for the JDK contained the same bug. It was reported to Sun recently when it broke someone's program, after lying in wait for nine years or so.” Not Really Sum could overflow!