Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling Workshop 10 - Data flow modeling Workshop 11 - Tasks and Functions Workshop 12 - Advanced Modeling Techniques Workshop 13 - Coding Styles and Test Benches

Signed data types For integer math operations, data types of the operands are used to determine if signed or unsigned arithmetic should be performed. To perform signed arithmetic, both operands must be signed. If any operand in an expression is unsigned, unsigned operations are performed. Verilog 1995 provides only one signed data type, 32bits integer. reg and net data types are unsigned. The rule still applies for Verilog 2001 but now all regs, wires and ports can be declared as signed. Sized numbers, bit and part select results and concatenation, yield unsigned values.

Signed arithmetic – Verilog 2001 extensions Verilog 2001 provides a new specifier, the letter ‘s’ that can be combined with the radix specifier to indicate that the literal number (sized value) is a signed value. For example, 2 represented as a 3-bit signed hex value would be specified as 3’sh2. Somewhat confusing is specifying negative signed values. The value -4 represented as a 3-bit signed hex value would be specified as -3’sh4. A decimal number is always signed. Function return values can be declared as signed. Type casting: Operands can be converted from unsigned to signed and vice versa, using system functions as casting operators, $unsigned and $signed.

Type Casting The casting operators, $unsigned & $signed, have effect only when casting a smaller bit width to a larger bit. Casting using $unsigned(signal_name) will zero fill the input. For example A = $unsigned(B) will zero fill B and assign it to A. Casting using $signed(signal_name) will sign extend the input. For example, A = $signed(B). If the sign bit is X or Z the value will be sign extended using X or Z, respectively.

Signed declarations examples reg signed [63:0] data ; wire signed [7:0] vector ; input signed [31:0] a ; function signed [128:0] alu ; integer i ; // 32 bit signed value B = 16'hC501 ; // an unsigned 16-bit hex value C = 16'shC501 ; // a signed 16-bit hex value reg [63:0] a; // unsigned data type always @(a) begin result1 = a / 2 ; //unsigned arithmetic result2 = $signed(a) / 2 ; //signed arithmetic end

Signed Addition and Signed Multiplication module add_signed_2001 ( // ANSI C Style Port Declarations input signed [2:0] A, input signed [2:0] B, output signed [3:0] Sum) ; assign Sum = A + B ; endmodule module mult_signed_2001 ( input signed [2:0] a, input signed [2:0] b, output signed [5:0] prod) ; assign prod = a*b ;

MIPS 5-stage pipeline Architecture

MIPS Instruction Set Architecture (ISA) R type instructions have opcode=0, address of 1st & 2nd operands, address of destination result, shift amount and function. I type instructions have opcode, address of 1 operand, address of destination result and a 16bits Constant (imm). Imm should be sign extended to 32bits signed number for addi. Imm should be zero extended to 32bits signed number for ori. Sh – 5bits shift amount for shift operations

MIPS Instructions Set Notes Format/Opcode/Func Meaning syntax Name Category Signed operands 20h R $d=$s+$t add $d,$s,$t Add Arithmetic 22h $d=$s-$t sub $d,$s,$t Sub - 8 I $t=$s+ C (signed) addi $t,$s,C Addi Unsigned operands 25h $d=$s|$t or $d,$s,$t Or Logical Dh $t = $s | C ori $t,$s,C Ori $d=$t<<sh sll $d,$t,sh Shleft logical Bitwise Shift 2 $d=$t>>sh srl $d,$t,sh Sright logical 3 $d=$t>>>sh sra $d,$t,sh Sright arithm

MIPS / ALU Instructions Instructions: Signed Operations: 1. add (signed) : result = in1 + in2 ; 2. sub (signed) : result = in1 - in2 ; 3. addi (signed) : result = in1 + imm ; Unsigned Operations: 4. or (bitwise logic) : result = in1 | in2 ; 5. ori (bitwise logic) : result = in1 | imm ; 6. shift left logical (sll): result = in2 << sh ; 7. shift right logical (srl): result = in2 >> sh ; 8. shift right arithmetic (sra): result = in2 >>> sh ;

Type casting in MIPS ALU Code module ALU ( ……. ) ; input signed [31:0] in1, in2, in3 ; // ALU input ports input [4:0] ALUop ; // ALU Operations code output [31:0] result ; // ALU computation result assign // continuous assignment – combinational logic result = (ALUop == Add) ? (in1 + in2) : (ALUop == Sub) ? (in1 - in2) : …………………………………….. // Type casting (ALUop == And) ? $unsigned(in1 & in2) : ………………………………. …………………………….. : 32’b0 ; // default=nop

MIPS Execution Unit Block Diagram 32 rf_do1 1st operand in1 shamt zero extend sh_extend ALU 32 5 1 32 extended shift amount result sel1 32 rf_do2 32 2nd operand in2 32 imm op z_s extend 1 16 Imm_extend 32 3 ctrl z_s sel2 ALUop

Exercise 8 MIPS ALU Design a limited functionality MIPS ALU module Implement the following Instructions: Signed Add, Add immediate, Sub. Use signed arithmetic. Bitwise Or, Or immediate. Unsigned. Shift left logical, Shift right logical, Shift right arithmetic, Unsigned. Use signed, negative number to demonstrate the difference between arithmetic & logical right shift. 4 X 4 Multiplier Design unsigned Multiplier, implemented as add-shift with 8bit adder. The 8bit adder to be implemented as ripple-carry adder, using eight 1_bit_full_adders.