Results of Heavy-Ion Broad and Micro Beam Testing of Flash Based FPGAs Radiation Testing SEFUW – Wednesday, September 17 th 2014 Adrian Evans, Dan Alexandrescu iROC Technologies – France Véronique Ferlet-Cavrois ESA-ESTEC – Netherlands

Outline  Background – ProASIC3L, SETs  SET Measurement Techniques  Results of Heavy Ion (HI) SET measurements (UCL)  HI Micro Beam Setup (GSI)  Results of Micro Beam Testing  Permanent Effects  Conclusions and Future Work

Background - ProASIC3L, SETs

SEFUW4 17-SEP-14 MicroSemi ProASIC3L A3PE3000L Core Voltage (V) Technology130nm, 7ML VeraTiles bit BRAMS112 CCC (including PLL)6 VersaNet Globals18 VersaTile One VersaTile can implement:  Any 3 input combinatorial function  A DFF or latch with options for preset, clear, enable  Configuration is controlled by floating gate switch

SEFUW5 17-SEP-14 Single Event Transients (SETs)  Upsets in combinatorial logic (VersaTiles)  Characterization requires :  Measuring rate of occurrence  Distribution of pulse widths  Function of :  VersaTile configuration (AND,OR, XOR, MAJ,…)  Input state  Voltage, Temperature  SETs in flash based FPGAs have been extensively studied [1..7]  New contributions : finer temporal resolution and complex circuits [1] S. Rezgui, et al., “New methodologies for set characterization and mitigation in flash Based FPGAs,” TNS’07, vol. 54, no. 6. [2] S. Rezgui, et al., “Configuration and routing effects on the set propagation in flash-based fpgas,” TNS’08, vol. 55, no.6. [3] C. Poivey, et al., “Radiation characterization of Microsemi Proasic3 flash FPGA Family,” REDW, [4] N. Battezzati, et al., “Analysis of SET Propagation in Flash-based FPGAs by means of electrical pulse injection,” RADECs [5] M. D. Berg, et al., “A comprehensive methodology for complex FPGA SEE Evaluation,” TNS’09, vol. 56. [6] L. Sterpone,et al. “Analysis of SET Propagation in flash-based FPGA by means of electrical pulse injection,” TNS’10, vol. 57. [7] L. Sterpone, et al., “An Analytical Model of PIPB on SETs in flash-based FPGAs,” TNS’11, vol. 58.

SET Measurement Techniques

SEFUW7 17-SEP-14 Existing SET Measurement Techniques  Pulse Filter [1,2] [1] S. Rezgui et al., “New methodologies for set characterization and mitigation in flash Based FPGAs,” TNS’07, vol. 54, no. 6. [2] S. Rezgui et al., “Configuration and routing effects on the set propagation in flash-based fpgas,” TNS’08, vol. 55, no.6. [3] L. Sterpone et al., “Analysis of SET Propagation in Flash_based FPGAs by means of Electrical Pulse Injection,” TNS’10, vol. 57, no.4  Off-chip measurement [3] Pad  Requires multiple filters to characterize pulse width distribution  Subject to on-chip delay variation (voltage, variability, etc.)  Resolution limited to 1 gate delay DUT SET Generation or Pulse Injection Digital Oscilloscope (DSO)  Subject to bandwidth of IO pads  Number of observations limited by available channels on DSO

SEFUW8 17-SEP-14 Vernier SET Measurement Technique (1)  Two latches are used to detect the SET (rising and falling edge)  Exploit the difference in delay along two chains for finer delay resolution  “Slow” delay chain (t1)  Triggered by rising (leading) edge of the transient  Feeds data input of transparent capture latches  “Fast” delay chain (t2)  Triggered by falling (trailing) edge of the transient  Feeds clock input of transparent capture latches  At each stage, the trailing edge catches up by (t2-t1) units of time  After a number of stages equal to PW / (t1-t2), the edges cross Slow Delay Chain Fast Delay Chain Capture Latches 1 Start Latch (rising edge) Stop Latch (falling edge)

SEFUW9 17-SEP-14 Vernier SET Measurement Technique (2)  Detector was designed with :  t1 ≈ 780 ps (AO1 VersaTile)  t2 ≈ 640 ps (BUF VersaTile)  36 stages  ≈ 140 ps delay resolution ; ≈ 5 ns maximum transient detection  Placement all done by “hand” (TcL scripts)  The detector is SEE robust  A valid event occurs only if both start and stop latches are triggered  The capture latches are normally open – not immune to upsets  Delays are calibrated prior to radiation testing  Each delay chain can be configured as a ring-oscillator and the frequency is measured

SEFUW10 17-SEP-14 SET Sensors (3 Topologies) Simple Chain of Gates Multiple Parallel Chains Tree Topology

SEFUW11 17-SEP-14 Full Device Under Test (DUT)  In total 92 different detectors integrated into one A3P3000L  Configuration logic and interrupt logic (DMR/TMR) used to multiplex detectors and report events

SEFUW12 17-SEP-14 SETs in Clocked Circuits  Objective is to measure SETs in clocked circuits (50 MHz)  Study commonly used combo circuits (adders, state-machine… )  Differentiate between SEUs and SETs  SEU={001,010,100} ; SET={110,101,011}  Measures “effective” impact of SET (post temporal, logical masking) Combinatorial NetworkPI / PO / VersaTiles 16-bit CLA Adder33 / 17 / bit priority encoder32 / 6 / 76 State machine logic25 / 12 / 63 4-bit, 8:1 MUX35 /4 / bit Hamming ECC Encoder16 / 5 / bit Hamming ECC Decoder21 / 16 /60 3 Copies Pairwise comparison: distinguish SEU vs. SET Pseudo-random vectors

Broad Beam HI Test Results (UCL)

SEFUW14 17-SEP-14 Voltage and LET  SETs are observed even at low LET (6.4 MeV * cm 2 / mg)  SET sensitivity reduces with higher voltage  At lower voltage (1.08V) increased t setup,t hold reduces detector sensitivity Lower voltage “apparent” lower sensitivity

SEFUW15 17-SEP-14 Pulse Broadening / Narrowing  Pulse broadening[1,2] was studied using gate chains of different length  In BUF VersaTiles, positive (0->1) transients are broadened and negative (1->0) transients are reduced in width Broadening – BUF (0->1) Narrowing – BUF (1->0) [1] V. Ferlet-Cavrois, et. al, “New insights into SET Propagation in Chains of Inverters; Evidence for PIPB,” TNS’07, vol. 54. [2] V. Ferlet-Cavrois, et al., “Investigation of the PIPB effect on SET in SOI and bulk inverter chains,” TNS’08, vol. 55. Ne : 6.4 MeV cm 2 /mg Ar : 16 MeV cm 2 /mg Kr : 40 MeV cm 2 /mg

SEFUW16 17-SEP-14 Variation Between VersaTiles  Characterization of a VersaTile presented as Cross Section (CS) versus pulse width  Measurement occurs at the output of detector chain (7x22 cells)  Measured pulse subject to broadening / narrowing  Significant variation based on input state Ne : 6.4 MeV cm 2 /mg Ar : 16 MeV cm 2 /mg Kr : 40 MeV cm 2 /mg OR2 IN = 00 MAJ3 IN = 110 MAJ3 IN = 100

SEFUW17 17-SEP-14 Temperature Effect  Little sensitivity in cross section or pulse width versus temperature

SEFUW18 17-SEP-14 Complex Circuits : Cross Section  Cross section has been normalized per-VersaTile (50 MHz operation)  Significant variation (nearly 10x) depending on circuit function Ne : 6.4 MeV cm 2 /mg Ar : 16 MeV cm 2 /mg Kr : 40 MeV cm 2 /mg

SEFUW19 17-SEP-14 Complex Circuits : Number of Affected Bits  Number of output bits that are affected by a single event  Even at low LET (6.4 Mev cm 2 /mg), multiple output bits can be affected  At higher LETs – multiple output upsets are frequent  Implications for parity protection techniques Ne : 6.4 MeV cm 2 /mg Ar : 16 MeV cm 2 /mg Kr : 40 MeV cm 2 /mg

Micro Beam Test Setup (GSI)

SEFUW21 17-SEP-14 GSI Heavy Ion Micro-Beam  Located in Darmstadt (near Frankfurt)  Individual ions launched at specific x-y positions  Beam is scanned over a region  16 μm x 16 μm  48 μm x 48 μm  144 μm x 144 μm  432 μm x 432 μm  500 nm resolution  Ions accelerated up to 11.4 MeV/μm  Au – 4.8MeV/μm - 94 MeV (mg/cm 2 )  Ti – 4.8 MeV/um - 19 MeV/(mg/cm 2 ) Opened A3P3000L

SEFUW22 17-SEP-14 Beam Control  User requests an ion (hit request)  GSI responds saying ion detected (gsi hit)  ions available in a 5ms burst every 200 ms  Typically repeat rate around ions / second Digilent Nexys 4 Xilinx Artix-7 Interface Card

1.Write pattern into memory. (~1.3 usec). 2.Read back pattern from memory + check. (~1.3 usec). 3.Wait for ions. (Handshaking). 4.Read back pattern from memory. (~1.3 usec). -> Report errors (macro, addr, bit) 5.Read back pattern from memory. (~1.3 usec). -> Report errors (macro, addr, bit) BRAM Test Flow

PLL Test Flow (On Chip Monitoring)  Basic idea sample CLK_UUT at 8x  At power-up, each sample point “locks” into position  4 / 8 sample points “lock”  Error if locked position moves (eg. edge moves ≥ 25% cycle) Reference PLL In : 50 MHz Out : 50,62.5,250 MHz PLL Under Test In : 50 MHz Output : 5 x (62.5 MHz) Locked (4/8)

PLL Test Flow (Off Chip Monitoring) Error Detect (trigger) PLL Output 1  To gain better insight into what is occurring when the PLL “error detector” triggers  External DSO samples 4 of 5 of the PLL outputs  Record signal trace if on-chip circuit triggers a PLL error PLL Output 2 PLL Output 3 PLL Output 4 Loss of Lock PLL UUT LeCroy WaveMaster DSO PLL Error Detector REF PLL

Micro Beam Test Results

 Logical Organization:  Two RAMs (U+L)  Each :512W x 9 bits Imaging of BRAM (1)

 Results from imaging with Au ions  Each color represents a bit cell  Note image from ion beam slightly rotated Imaging of BRAM (2)

 Zoomed in scan on BRAM region – Au ions  Bit cells overlap – not possible to identify shape of bit cells 48um 38um Imaging of BRAM (3) Coloured dots represent bit cells White dots represent points with no response 48um 38um

 BRAM image produced using Ti ions  Colours represent individual bit cells  Shape of bit cell can be discerned (e.g. vertical mirroring)  Logic to physical mapping has been extracted Imaging of BRAM (4) BRAM – All zeroesBRAM – All ones

PLL Imaging (Au Ions) Purple = 5 outputs glitchPink = 1..4 outputs glitch Dark Blue = Loss of lock ONLYYellow = Loss of lock + output glitches

PLL Imaging (Ti Ions) Purple = 5 outputs glitchPink = 1..4 outputs glitch Dark Blue = Loss of lock ONLYYellow = Loss of lock + output glitches  Many cases where clocks glitch but no loss of lock  From external captures, appears clock disappears for a handful of clock cycles

SEFUW33 17-SEP-14 Permanent Effects  Devices were re-programmed with beam OFF  During broad beam testing (UCL)  One device failed to re-program after 1.37 part/cm 2 of Xe ions (≈4.2Krad)  Others failed after longer exposure  During micro-beam testing (GSI)  One device failed to re-program after ≈1000 Au ions  Messages were “Verification 0 failed at rows 7843”  Devices appeared to function correctly if verification disabled  Subsequent to the testing, some of the devices damaged at UCL could be successfully programmed at being annealed at 100°C for four days  More work required to understand this effect (not focus of current work)

Conclusions and Future Work

SEFUW35 17-SEP-14 Conclusions  Characterization of SETs is complex  Dependent on : VersaTile configuration, input state, propagation  Vernier detector - good sensitivity and temporal precision  SET characterization of complex circuits more exploitable  HI micro-beam highly effective tool for investigating sensitive regions  Selection of ion energy is important for resolution  Setup of experiments and data logging is complex

SEFUW36 17-SEP-14 Future and Ongoing Work  Complete data analysis for GSI experiments  Extend SET measurement circuits to characterize ASIC standard cells  Continue investigation of destructive effects

SEFUW37 17-SEP-14 Questions? Thank You!