VLSI Design & Embedded Systems Conference January 2015 Bengaluru, India Diagnostic Tests for Pre-Bond TSV Defects Bei Zhang Vishwani Agrawal

Purpose of Pre-bond TSV Test 7/2/2015© VLSI Design & Embedded Systems Conference  Defects arise in TSV manufacturing. Pre- bond TSV test helps identify defective dies early in the process.  Pre-bond TSV test provides known good die (KGD) information for die-on-die or die-on- wafer or wafer-on-wafer fabrication process.

Outline 3D IC Structure and TSV Models Pre-bond TSV Probing technique Test Session Generation Experimental Results Conclusion 7/2/2015© VLSI Design & Embedded Systems Conference

4 TSV-based 3D IC Structure 3D face-to-back stacked IC: 7/2/2015© VLSI Design & Embedded Systems Conference

RC Models of Defective TSVs After Wafer Thinning 7/2/2015© VLSI Design & Embedded Systems Conference Resistance-defective TSVCapacitance-defective TSV B. Noia and K. Chakrabarty, Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs. Springer, 2014.

Illustration of Pre-bond TSV Probing on the Substrate Side 7/2/2015© VLSI Design & Embedded Systems Conference GSF: Gated scan flip-flop

Circuit Model of Pre-bond TSV Test 7/2/2015© VLSI Design & Embedded Systems Conference

7/2/2015© VLSI Design & Embedded Systems Conference Circuit Model of Pre-bond TSV Test

7/2/2015© VLSI Design & Embedded Systems Conference Circuit Model of Pre-bond TSV Test

7/2/2015© VLSI Design & Embedded Systems Conference Circuit Model of Pre-bond TSV Test

Capacitor Charging Time Through Parallel TSVs 7/2/2015© VLSI Design & Embedded Systems Conference Number of TSVs charging in parallel (q) Capacitor charging time t(q) (μs) S. K. Roy, S. Chatterjee, C. Giri, and H. Rahaman, “Faulty TSVs Identification and Recovery in 3D Stacked ICs During Pre-bond Testing,” Proc. International 3D Systems Integration Conference, 2013, pp. 1–6.

Two Important Observations 1) Any faulty TSV within a parallel test will cause the test to fail but we cannot tell which TSV(s) is (are) faulty. 2) A good parallel test implies that all TSVs within the parallel test are fault-free. 7/2/2015© VLSI Design & Embedded Systems Conference

Terminology 7/2/2015© VLSI Design & Embedded Systems Conference TSV networkTSVs simultaneously contacted by probe. Test session (S i )TSVs grouped for parallel charging of capacitor. Maximum number of faulty TSVs in network (m) m is the number of redundant TSVs within the TSV network. Session size (q)q is the number of active TSVs within a session. Resolution (r)r is an upper bound on session size. Test time of a session (t(q)) Charging time of C charge, related to session size. Fault map (ρ)Fault map represents positions of defective TSVs within the TSV network.

Test Session Generation  Motivation Compared to individual TSV test, large test time saving is possible if we test TSVs in parallel without losing the capability of identifying up to m faulty TSVs, while guaranteeing that the size of each test session does not exceed the resolution constraint r. 7/2/2015© VLSI Design & Embedded Systems Conference

Test Session Generation  Problem Statement Given: Test times t(q) for different session sizes q (q ∈ [1, r]), and Maximum number (m) of faulty TSVs in a network of T TSVs. Determine: A set of test sessions of size less than r, such that up to m faulty TSVs are uniquely identified and the total test time is minimized. 7/2/2015© VLSI Design & Embedded Systems Conference

Test Session Generation  Sufficient condition If each TSV i is included in m + 1 sessions (say, S 1, S 2, · · ·, S m+1 ) and the intersection of a pair of these m + 1 sessions contains only TSV i, i.e., S i ∩ S j = TSV i for i ≠ j ∈ [1, m + 1], then up to m faulty TSVs within the network can be uniquely identified. These m + 1 sessions are called unique test sessions for TSV i. 7/2/2015© VLSI Design & Embedded Systems Conference B. Noia and K. Chakrabarty, “Identification of Defective TSVs in Pre-Bond Testing of 3D ICs,” Proc. 20th Asian Test Symposium (ATS), 2011, pp. 187–194.

A Previous Heuristic Method To pinpoint 1 faulty TSV in a 6-TSV network with resolution constraint r = 4, the heuristic-based sessions are {1,2,3,4}, {1,5,6}, {2,5}, {3,6}, {4}. Careful examination shows: Each TSV resides in two unique test sessions! The heuristic sessions reduce the total test time compared to individual TSV testing. 7/2/2015© VLSI Design & Embedded Systems Conference B. Noia and K. Chakrabarty, “Identification of Defective TSVs in Pre-Bond Testing of 3D ICs,” Proc. 20th Asian Test Symposium (ATS), 2011, pp. 187–194.

Limitation of the Heuristic Method  Sessions {1,2,3,4}, {1,5,6}, {2,5}, {3,6}, {4} are not optimal. The optimal set of sessions are {1,2,3}, {1,4,5}, {2,4,6}, {3,5,6}  As we can see every TSV still resides in 2 unique sessions, but the total test time is further reduced by 36.8%! 7/2/2015© VLSI Design & Embedded Systems Conference

ILP based Session Generation  Three general constraints for ILP model (ILP model 1): C1. Each TSV should be included in at least m + 1 test sessions. C2. The size of a test session ranges anywhere from 0 (empty session) to r. C3. Any non-empty session is supposed to be a unique session for any TSV within it.  Objective: Minimize total test time of all sessions. 7/2/2015© VLSI Design & Embedded Systems Conference

Experimental Results 7/2/2015© VLSI Design & Embedded Systems Conference Test time comparison for a 20-TSV network

Experimental Results 7/2/2015© VLSI Design & Embedded Systems Conference Test time comparison for resolution constraint r = 3

Experimental Results 7/2/2015© VLSI Design & Embedded Systems Conference Comparison of number of sessions for r = 4

Conclusion 7/2/2015© VLSI Design & Embedded Systems Conference An ILP model is proposed to generate near- optimal set of test sessions for pre-bond TSV testing. ILP model always reduces pre-bond TSV identification time compared to that of a previous heuristic method. Future exploration can be possibly deriving necessary and sufficient conditions to generate globally optimal set of sessions.