© Digital Integrated Circuits 2nd Sequential Circuits Cascading Dynamic Gates  Dynamic gates rely on temporary capacitive storage, while static gates have DC restoration.  Except the above design issues, there is one major catch that complicates the design of dynamic circuits: straight-forward cascading of dynamic gates to create multi-level logic does NOT work.

© Digital Integrated Circuits 2nd Sequential Circuits Cascading Dynamic Gates Clk Out1 In MpMp MeMe MpMp MeMe Clk Out2 V t ClkIn Out1 Out2 VV V Tn 1) The arises because the outputs of each gate – thus the inputs of the next gate – are all precharged to 1, which may cause inadvertent discharge in the beginning of evaluation cycle. 2) Setting all inputs (to next gates) to 0 during precharge address that concern. So, only 0  1 transitions allowed at inputs !

© Digital Integrated Circuits 2nd Sequential Circuits Domino Logic – NMOS dynamic gate with static inverter In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PDN In 5 MeMe MpMp Clk Out2 M kp 1  1 1  0 0  0 0  1 Additional advantage of introducing an inverter (low impedance of gate, smaller delay) Bleeder device

© Digital Integrated Circuits 2nd Sequential Circuits Why Domino? – like falling dominos Clk In i PDN In j In i In j PDN In i PDN In j In i PDN In j

© Digital Integrated Circuits 2nd Sequential Circuits Properties of Domino Logic  Only non-inverting logic can be implemented  Since each dynamic gate has a static inverter  Very high speed  Only H-L delay exists (L-H transition equal to 0)  Input capacitance reduced – smaller logical effort (since each fanout needs to connect to NMOS only compared to static CMOS logic)

© Digital Integrated Circuits 2nd Sequential Circuits Designing with Domino Logic M p M e V DD PDN Clk In Out1 Clk M p M e V DD PDN Clk In 4 Clk Out2 M r V DD All Inputs = 0 during precharge Can be eliminated?

© Digital Integrated Circuits 2nd Sequential Circuits Footless Domino 1) Without evaluation devices, when the first gate goes to precharge, the second gate has to wait for In2 to get to 0 since it fights against the precharge, which takes two inverter delays. More delay for later gates. 2) This also causes short circuit power consumption

© Digital Integrated Circuits 2nd Sequential Circuits Differential (Dual Rail) Domino A B MeMe MpMp Clk Out = AB !A!B M kp Clk Out = AB M kp MpMp Solves the problem of non-inverting logic, similar concept as DCVSL 1 0 It is actually used in a few commercial microprocessors (like DEC Alpha E series processors)!

© Digital Integrated Circuits 2nd Sequential Circuits Both the logic and its inverse are simultaneously implemented

© Digital Integrated Circuits 2nd Sequential Circuits np-CMOS Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN PDN can follow PUN and vice versa In 1 In 2 PDN In 3 MeMe MpMp Clk Out1 In 4 PUN In 5 MeMe MpMp Clk Out2 (to PDN) 1  1 1  0 0  0 0  1 To other N-blocks To other P-blocks

© Digital Integrated Circuits 2nd Sequential Circuits np-CMOS  One dis-advantage is that P-blocks are slower than N- blocks due to low current driving strengths of PMOS (equalizing the delay imply more area)  May cause larger power consumption due to differential logic

© Digital Integrated Circuits 2nd Sequential Circuits Summary of logic styles  We have discussed Static complementary, Ratioed, Pass transistor and Dynamic logic styles  Which one to use strongly depends on the following factors: ease of design, robustness, area, power and speed.  No single style optimize all these metrics  Current trend is towards an increased use of complementary static CMOS logic style (somewhat due to the use of design automation tools at logic design level which requires that the logic be robust and complexity problem). Also, static CMOS is more amenable to voltage scaling.

© Digital Integrated Circuits 2nd Sequential Circuits Future trends  To use multiple threshold transistors, low threshold for performance critical circuits and high-threshold for leakage control.  To dynamically adjust the threshold of transistor by adaptively controlling the body effect.  Voltage islands: different voltage at different blocks.

© Digital Integrated Circuits 2nd Sequential Circuits Layout techniques for complex gates

© Digital Integrated Circuits 2nd Sequential Circuits Layout preference  For layout density, it is desirable to realize NMOS and PMOS transistors as an unbroken row of devices with abutting source-drain connections and with gate connections of NMOS and PMOS aligned.  For this, it requires only a single strip of diffusion in both wells.  To achieve the goal, a careful ordering of input terminals is necessary.

© Digital Integrated Circuits 2nd Sequential Circuits Stick Diagrams for layout Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A Out V DD GND B NAND2

© Digital Integrated Circuits 2nd Sequential Circuits Two Versions of C (A + B) X CABABC X V DD GND V DD GND Two strips of diffusion

© Digital Integrated Circuits 2nd Sequential Circuits Layout planning using Euler Path  A systematic approach has been developed to derive the permutation of input terminals so that complex functions can be realized by un-interrupted diffusion strips that minimize the area.  The approach has two steps, construction of logic graph and identification of Euler paths.  The logic graph of a logic function is a graph of which the vertices are the signals of the network and the edges are the transistors.  An Euler path is defined as a path through all nodes in the graph such that each edge is only visited once.  The Euler paths for PDN and PUN must be the same in order to use a single poly for each input signal

© Digital Integrated Circuits 2nd Sequential Circuits Stick Diagrams C AB X = C (A + B) B A C i j j V DD X X i GND AB C PUN PDN A B C Logic Graph

© Digital Integrated Circuits 2nd Sequential Circuits Consistent Euler Path j V DD X X i GND AB C ABC

© Digital Integrated Circuits 2nd Sequential Circuits OAI22 Logic Graph C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D

© Digital Integrated Circuits 2nd Sequential Circuits Example: x = ab+cd

© Digital Integrated Circuits 2nd Sequential Circuits Notes  The above layout technique is for single finger transistors.  When it comes to one strip of diffusion but with each transistor having multiple fingers, layout further complicate and you may still be able to do so.

© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Revised from Digital Integrated Circuits, © Jan M. Rabaey el

© Digital Integrated Circuits 2nd Sequential Circuits Sequential Logic 2 storage mechanisms positive feedback charge-based

© Digital Integrated Circuits 2nd Sequential Circuits Naming Conventions  In our text:  a latch is level sensitive  a register is edge sensitive  There are many different naming conventions  For instance, many books call edge- triggered elements flip-flops  This leads to confusion however

© Digital Integrated Circuits 2nd Sequential Circuits Memory elements  At high level, memory is classified as background memory and foreground memory.  Memory that is embedded into logic is foreground memory.  Large amounts of centralized memory core is background memory, which achieves higher area density through efficient use of array structures.  Here, we focus on foreground memory elements here.

© Digital Integrated Circuits 2nd Sequential Circuits Latch versus Register  Latch stores data when clock is high or low D Clk Q D Q  Register stores data when clock rises or falls Clk D D QQ

© Digital Integrated Circuits 2nd Sequential Circuits Latches

© Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

© Digital Integrated Circuits 2nd Sequential Circuits Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ T setup : setup time is the time that data input D must be valid before clock transition T hold : hold time is the time that data input D must remain valid after the clock edge T c2q : propagation delay of copying D to Q output

© Digital Integrated Circuits 2nd Sequential Circuits Characterizing Timing Register Latch C2Q with respect to clock, D2Q to input signal

© Digital Integrated Circuits 2nd Sequential Circuits Maximum Clock Frequency Also another constraint: t cd,reg + t cd,logic > =t hold t cd : contamination delay = minimum delay This constraint ensures the input data of the sequential circuits is held long enough after the clock edge and not modified too soon by the new coming-in data t c2q + t p,comb + t setup <= T Clock period T must accommodate the longest possible delay

© Digital Integrated Circuits 2nd Sequential Circuits Positive Feedback: Bi-Stability V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1 When the gain of inverter in transient region is larger than 1, A & B are the only stable operating points, C is metastable.

© Digital Integrated Circuits 2nd Sequential Circuits Meta-Stability Gain should be larger than 1 in the transition region Hence, cross coupling of two inverters results in a bistable circuit, that is a circuit with two stable states. The circuit serves as a memory, storing either a 1 or 0 (A or B)

© Digital Integrated Circuits 2nd Sequential Circuits Bistable circuit Bistable circuit  In absence of triggering, a bistable circuit remains in a single state (static memory as long as power is on). Another common name for a bistable circuit is flip-flop  A FF is only useful when there is a mean to bring it from one state to the other one.  Two approaches can achieve that:  cutting the feedback loop, once the feedback loop is open, a new value can be written. This is called multiplexer based.  Overpowering the feedback loop, by applying a trigger signal at the input of the FF, a new value is forced into the circuit by overpowering the previous stored value.

© Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q