© H. Heck 2008Section 4.31 Module 4:Metrics & Methodology Topic 3: Source Synchronous Timing OGI EE564 Howard Heck

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.32 Where Are We? 1.Introduction 2.Transmission Line Basics 3.Analysis Tools 4.Metrics & Methodology 1.Synchronous Timing 2.Signal Quality 3.Source Synchronous Timing 4.Recovered Clock Timing 5.Design Methodology 5.Advanced Transmission Lines 6.Multi-Gb/s Signaling 7.Special Topics

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.33 Contents Synchronous Bus Limitations Source Synchronous Concept & Advantages Operation Timing Equations Maximum Transfer Rate Summary References Appendix: Timing Equation Derivation

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.34 Common Clock Limitations Max frequency is defined by min cycle time Min cycle time is limited by maximum delays. Can we find a way to remove the dependence on absolute delays? clk D Q CLK D Q ab FROM CORE TO CORE

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.35 Source Synchronous Signaling Concept The transmitting agent sends the clock (a.k.a. strobe), along with the data signal. Overview: Drive the clock and data signals with a known phase relationship. Design the clock and data signals to be identical in order to preserve the phase relationship. As long as the phase relationship can be maintained, the lines can be much longer.

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.36 Suppose that we transmit a data signal 1 ns prior to transmitting the strobe. You’re given a 500 ps receiver setup requirement. You find that the flight time for the data signal varies between 5.5 ns and 5.7 ns. The flight time for the clock signal also varies between 5.5 ns and 5.7 ns, independent from the data. Can we meet the setup requirement? Source Synchronous Concept Example Tx Tx Rx Rx T su = 500 ps 5.7 ns 5.5 ns 1.0 ns 300 ps

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.37 Source Synchronous Advantage From the preceding example, it should be apparent that source synchronous performance depends on relative, rather than absolute delays. True for drivers and interconnect, though we must still meet the absolute setup/hold requirements for the receiver. In real systems, the difference in delay between signals can be made much smaller than the absolute delays. Therefore, with source synchronous signaling we can expect to achieve higher performance to be able to use longer traces

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.38 Transfer Rate Comparison Synchronous Source Synchronous FSB200 MHz1600 MT/s Graphics66 MHz533 MT/s Memory133 MHz 1600 MT/s 800 MT/s (RDRAM)

Source Synchronous Timing EE 564 © H. Heck 2008 Section 4.39 Operation Typically, there is one strobe signal (or pair of signals) per two bytes of data signals. Varies by design Signal relationships at the transmitter are shown below.

Source Synchronous Timing EE 564 © H. Heck 2008 Section Source Synchronous Operation T va T vb ThTh T su T suskew STROBE/STROBE DATA T hmar T hskew T sumar RECEIVER T suskew : flight time skew for setup T sumar : setup margin T vb : min driver phase offset (setup) T hskew : flight time skew for hold T hmar : hold margin T va : min driver phase offset (hold)

Source Synchronous Timing EE 564 © H. Heck 2008 Section Source Synchronous Equations T va T vb ThTh T su T suskew STROBE/STROBE DATA T hmar T hskew T sumar RECEIVER The sum of the timings at the receiver must not exceed the phase offsets at the driver:  the transmitter design requires minimum offsets: [4.3.1][4.3.2] [4.3.3][4.3.4]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Source Synchronous Equations #2 We must also satisfy the following relationship: This determines our maximum transfer rate. T bit : data bit width TR max : max transfer rate [4.3.6] [4.3.5] T va T vb ThTh T su T suskew STROBE/STROBE DATA T hmar T hskew T sumar RECEIVER

Source Synchronous Timing EE 564 © H. Heck 2008 Section Question Based on what we’ve covered in the previous slides, what are the implications to:  The transmitter design?  The receiver design?  The interconnect design?

Source Synchronous Timing EE 564 © H. Heck 2008 Section Example T su = 500 ps, T h = 500 ps The target transfer rate is 500 MT/s. What are reasonable flight time skew targets?

Source Synchronous Timing EE 564 © H. Heck 2008 Section Source Synchronous Timing Summary Synchronous timings are limited by absolute delays. Source synchronous timings use a strobe eliminate dependence on absolute delay.  Performance depends on our ability to maintain known phase relationship between data & strobe As a result, source synchronous interfaces typically operate at 2x-8x the clock frequency.  Expect that ratio to scale much higher in the future. Matching of delays (transmitter & interconnect) is a key design consideration for designing high speed source synchronous interfaces.

Source Synchronous Timing EE 564 © H. Heck 2008 Section References S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1 st edition. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1 st edition, H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.

Source Synchronous Timing EE 564 © H. Heck 2008 Section Appendix: Source Synchronous Timing Equation Derivation

Source Synchronous Timing EE 564 © H. Heck 2008 Section Source Synchronous Bus Operation

Source Synchronous Timing EE 564 © H. Heck 2008 Section Operation #2 The transmitted strobe (and data) signals are generated from the on-chip bus clock. Typically, the strobe is phase shifted by ½ cycle from the data signal.  Duty cycle variations will cause variation on the phase relationship The timing path starts at the flip-flop of the transmitting agent and ends at the flip- flop of the receiving agent. The strobe signal is used as the clock input of the receiver flip-flop.

Source Synchronous Timing EE 564 © H. Heck 2008 Section Setup Timing Diagram & Loop Analysis T co (STB) T sumar DCLK T BCLK /4 T BCLK BCLKSTB/STBDRIVERDATADRIVER DATARECEIVER STB/STB T flight (DATA) T su T co (DATA) t T flight (STB) [4.3.1a]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Setup Analysis For a “double pumped” bus, the difference between T co (DATA) and T co (STB) is typically set to one-half of the cycle time ( T DCLK /2 = T BCLK /4) to center the strobe in the data valid window.  Double pumped: source synchronous transfer rate is 2x the central clock rate. This relationship is typically specified as T vb (data “valid before” strobe ), which signifies the minimum time for which the data at the transmitter is valid prior to transmission of the strobe. Mathematically: Simplify the loop equation: [4.3.1a] [4.3.2a] [4.3.3a]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Setup Analysis #2 Both data & strobe propagate over the interconnect.  Goal: identical flight times. In reality, there will be some difference in flight times between data and strobe.  trace length, loading, crosstalk, ISI, etc. Define flight time skew for the setup condition: Simplify the loop equation: [4.3.4a] [4.3.5a] [4.3.6a]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Notes on the Setup Equation You may see the timing equation written in other forms. The way I defined T vb makes it a negative quantity. Others may define it to be positive. I defined T suskew to be a positive quantity. [4.3.7a]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Hold Timing Diagram & Loop Analysis t DATADRIVER DCLK T flight (STB) T co (STB) T co (DATA) ThTh T hma r DATARECEIVER T BCLK /4 BCLK T BCLK STB/STBDRIVER RECEIVERSTB/STB T flight (DATA)

Source Synchronous Timing EE 564 © H. Heck 2008 Section Hold Analysis Just as for the setup case, we need to specify the minimum phase relationship between data and strobe: In addition, define the flight time skew for the hold case: Note that the T hskew is defined such that it is a negative quantity, while T va is defined to be positive. [4.3.8a] [4.3.9a] [4.3.10a] [4.3.11a]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Maximum Transfer Rate The maximum transfer rate can be determined using the definitions for T va and T vb. We can calculate the limit of T BCLK (for a double pumped bus) by adding the two equations above. DATA T va,min STB/STB -T vb,min T cycle,min [4.3.12a]

Source Synchronous Timing EE 564 © H. Heck 2008 Section Higher Transfer Rates (e.g. “Quad Pumped”) The setup and hold equations remain the same. What changes are the T va and T vb definitions: [4.3.13a] [4.3.14a]