Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 8 Computer Arithmetic.

Slides:



Advertisements
Similar presentations
Lecture 11 Oct 12 Circuits for floating-point operations addition multiplication division (only sketchy)
Advertisements

Computer Engineering FloatingPoint page 1 Floating Point Number system corresponding to the decimal notation 1,837 * 10 significand exponent A great number.
Lecture 16: Computer Arithmetic Today’s topic –Floating point numbers –IEEE 754 representations –FP arithmetic Reminder –HW 4 due Monday 1.
Princess Sumaya Univ. Computer Engineering Dept. Chapter 3:
Princess Sumaya Univ. Computer Engineering Dept. Chapter 3: IT Students.
Datorteknik FloatingPoint bild 1 Floating point Number system corresponding to the decimal notation 1,837 * 10 significand exponent a great number of corresponding.
Chapter 3 Arithmetic for Computers. Multiplication More complicated than addition accomplished via shifting and addition More time and more area Let's.
Integer Arithmetic Floating Point Representation Floating Point Arithmetic Topics.
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji.
COE 308: Computer Architecture (T041) Dr. Marwan Abu-Amara Integer & Floating-Point Arithmetic (Appendix A, Computer Architecture: A Quantitative Approach,
CPSC 321 Computer Architecture ALU Design – Integer Addition, Multiplication & Division Copyright 2002 David H. Albonesi and the University of Rochester.
ECEN 248 Integer Multiplication, Number Format Adopted from Copyright 2002 David H. Albonesi and the University of Rochester.
Computer ArchitectureFall 2008 © August 27, CS 447 – Computer Architecture Lecture 4 Computer Arithmetic (2)
3-1 Chapter 3 - Arithmetic Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Computer Architecture.
Data Representation – Binary Numbers
Computer Organization and Architecture Computer Arithmetic Chapter 9.
Computer Arithmetic. Instruction Formats Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than.
Computer Architecture Lecture 3: Logical circuits, computer arithmetics Piotr Bilski.
ECE232: Hardware Organization and Design
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /14/2013 Lecture 16: Floating Point Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE.
Oct. 18, 2007SYSC 2001* - Fall SYSC2001-Ch9.ppt1 See Stallings Chapter 9 Computer Arithmetic.
Computer Arithmetic II Instructor: Mozafar Bag-Mohammadi Spring 2006 University of Ilam.
1 Binary Coded Decimal Presented By Chung Wai Chow.
Fixed and Floating Point Numbers Lesson 3 Ioan Despi.
Computer Arithmetic II Instructor: Mozafar Bag-Mohammadi Ilam University.
Lecture 12: Integer Arithmetic and Floating Point CS 2011 Fall 2014, Dr. Rozier.
Conversion to Larger Number of Bits Ex: Immediate Field (signed 16 bit) to 32 bit Positive numbers have implied 0’s to the left. So, put 16 bit number.
Princess Sumaya Univ. Computer Engineering Dept. Chapter 3:
Lecture notes Reading: Section 3.4, 3.5, 3.6 Multiplication
Computer Engineering FloatingPoint page 1 Floating Point Number system corresponding to the decimal notation 1,837 * 10 significand exponent A great number.
Chapter 3 Arithmetic for Computers. Chapter 3 — Arithmetic for Computers — 2 Arithmetic for Computers Operations on integers Addition and subtraction.
Floating Point Numbers Representation, Operations, and Accuracy CS223 Digital Design.
Computer Architecture Lecture 11 Arithmetic Ralph Grishman Oct NYU.
CS 232: Computer Architecture II Prof. Laxmikant (Sanjay) Kale Floating point arithmetic.
Chapter 8 Computer Arithmetic. 8.1 Unsigned Notation Non-negative notation  It treats every number as either zero or a positive value  Range: 0 to 2.
S 2/e C D A Computer Systems Design and Architecture Second Edition© 2004 Prentice Hall Chapter 6 Overview Number Systems and Radix Conversion Fixed point.
1. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami2 Figure 11.1 Multiplication of 4-bit numbers in dot notation.
Arithmetic for Computers Chapter 3 1. Arithmetic for Computers  Operations on integers  Addition and subtraction  Multiplication and division  Dealing.
William Stallings Computer Organization and Architecture 8th Edition
Floating Point Representations
COMPUTER ARITHMETIC Arithmetic with Signed-2's Complement Numbers
Array multiplier TU/e Processor Design 5Z032.
Computer Architecture & Operations I
Morgan Kaufmann Publishers Arithmetic for Computers
Floating Point Number system corresponding to the decimal notation
CS 232: Computer Architecture II
Expressible Numbers.
Arithmetic for Computers
Outline Introduction Floating Point Arithmetic Adder Multiplier.
ECE/CS 552: Floating Point
CSCE 350 Computer Architecture
Arithmetic Logical Unit
How to represent real numbers
How to represent real numbers
ECEG-3202 Computer Architecture and Organization
Chapter 8 Computer Arithmetic
Chapter 6: Computer Arithmetic
Digital System Design II 数字系统设计2
Morgan Kaufmann Publishers Arithmetic for Computers
Chapter 4 計算機算數.
Presentation transcript:

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 8 Computer Arithmetic

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Unsigned notationsUnsigned notations Signed notationsSigned notations Binary Coded DecimalBinary Coded Decimal Specialized arithmetic hardwareSpecialized arithmetic hardware Floating point numbersFloating point numbers IEEE 754 floating point standardIEEE 754 floating point standard

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Unsigned Notations Unsigned non-negativeUnsigned non-negative Unsigned two’s-complementUnsigned two’s-complement

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Unsigned Notations Unsigned non-negativeUnsigned non-negative Unsigned two’s-complementUnsigned two’s-complement

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Addition: X  X + Y

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Overflow

Subtraction: X  X - Y

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Overflow

Multiplication A non-optimal methodA non-optimal method z = 0 FOR i = 1 TO y DO { z = z + x }

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication A more typical methodA more typical method

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication Calculating running totalsCalculating running totals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication Shifting partial results to align sumsShifting partial results to align sums

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Shift-add Multiplication Algorithm C = 0, U = 0;

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example: UV  X  Y (X = 1101, Y = 1001) C = 0, U = 0 0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code C  0, U  0, i  n

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example: UV  X  Y (X = 1101, Y = 1001) C  0, U  0, i  4 0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Hardware Implementation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimizing the RTL Code UV  X  VUV  X  V Register Y not neededRegister Y not needed One operand is lostOne operand is lost

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimizing the RTL Code C  0, U  0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example C  0, U  0, i  4 0

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Booth’s Algorithm Multiplying unsigned 2’s-complement numbersMultiplying unsigned 2’s-complement numbers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example UV  X  Y, X = -3 (1101), Y = -5 (1011)UV  X  Y, X = -3 (1101), Y = -5 (1011)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example UV  X  Y, X = -3 (1101), Y = -5 (1011)UV  X  Y, X = -3 (1101), Y = -5 (1011)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Optimized RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Hardware Implementation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Division A non-optimal methodA non-optimal method

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Division A more typical methodA more typical method

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Division Shifting results to align remaindersShifting results to align remainders

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Shift-subtract Division Algorithm

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example: UV  X (UV = , X = 1101)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Hardware Implementation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Restoring Division Algorithm

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Overflow Comparison

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Hardware Implementation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Signed Notations Signed-magnitudeSigned-magnitude

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Signed Notations Signed-magnitudeSigned-magnitude Signed-2’s complementSigned-2’s complement

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Signed Notations Signed-magnitudeSigned-magnitude Signed-2’s complementSigned-2’s complement Value Signed-magnitude Signed-2’s complement

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Addition and Subtraction

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Examples

Examples

Examples

Hardware Implementation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication

Example

Binary Coded Decimal (BCD) Every 4 bits = 1 decimal digitEvery 4 bits = 1 decimal digit 1 bit sign1 bit sign Example: +27 = Example: +27 =

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 BCD Adder

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Nine’s Complement Equivalent of 1’s complement in binaryEquivalent of 1’s complement in binary

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Nine’s Complement Equivalent of 1’s complement in binaryEquivalent of 1’s complement in binary

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Examples

Examples

Examples

Hardware Implementation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication dshr: decimal shift rightdshr: decimal shift right

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication dshr: decimal shift rightdshr: decimal shift right

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Arithmetic Pipelines Increase throughputIncrease throughput

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Arithmetic Pipelines Increase throughputIncrease throughput Speedup:Speedup:

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Example

Example

Steady State Speedup

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Steady State Speedup

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speedup with Latch Delays

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Speedup with Latch Delays

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Lookup Tables

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Wallace Trees Carry Save AdderCarry Save Adder

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Wallace Trees Carry Save AdderCarry Save Adder

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Wallace Trees Partial productsPartial products

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Wallace Trees Partial productsPartial products

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Example

4  4 Wallace Tree

Images courtesy of Addison Wesley Longman, Inc. Copyright ©  8 Wallace Tree

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Floating Point Numbers Sign, Significand, ExponentSign, Significand, Exponent Normalized:Normalized: =  =  10 4 NaNNaN BiasingBiasing

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Floating Point Numbers PrecisionPrecision GapGap RangeRange Round, Guard, Sticky bitsRound, Guard, Sticky bits

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Rounding Round toward nearestRound toward nearest Round toward 0Round toward 0 Round toward + Round toward +  Round toward - Round toward - 

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example

Addition and Subtraction

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Addition and Subtraction

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example: (.1101  2 3 ) + (.1110  2 2 )

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example: (.1101  2 3 ) - (.1110  2 2 )

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Multiplication Check for special valuesCheck for special values Add exponentsAdd exponents Multiply significandsMultiply significands Normalize resultNormalize result

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 RTL Code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Example: (.1101  2 3 )  (.1110  2 2 )

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IEEE 754 Floating Point Standard 1  significand < 21  significand < 2 Single of double precisionSingle of double precision

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IEEE 754 Floating Point Standard IEEE 754 Floating Point Standard

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 IEEE 754 Floating Point Standard

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Denormalized Values Used to express smaller numbers than possible with normalized notationUsed to express smaller numbers than possible with normalized notation Smallest normalized value: (single precision)Smallest normalized value: (single precision) Smallest denormalized value: (single precision)Smallest denormalized value: (single precision)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Unsigned notationsUnsigned notations Signed notationsSigned notations Binary Coded DecimalBinary Coded Decimal Specialized arithmetic hardwareSpecialized arithmetic hardware Floating point numbersFloating point numbers IEEE 754 floating point standardIEEE 754 floating point standard