Salman Zaffar IqraUniversity, Spring 2012

Slides:

Advertisements

Similar presentations

EE466: VLSI Design Lecture 7: Circuits & Layout

Advertisements

COMBINATIONAL LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

S.N.Bhat, Faculty, Dept. of E&C Engineering, M.I.T Manipal

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris lecture.

CMOS Layers n-well process p-well process Twin-tub process ravikishore.

MICROELETTRONICA CMOS THEORY Lezione 2.

EE 414 – Introduction to VLSI Design

Lecture 0: Introduction

VLSI Design Circuits & Layout

Lecture 1: Circuits & Layout

Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley]

Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout

Introduction to CMOS VLSI Design Lecture 0: Introduction

Prelab: MOS gates and layout

Combinational MOS Logic Circuit

VLSI Design Circuits & Layout

Introduction to CMOS VLSI Design Lecture 0: Introduction

Design and Implementation of VLSI Systems (EN1600) lecture05 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Introduction to CMOS VLSI Design Circuits & Layout

Introduction Integrated circuits: many transistors on one chip.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

Introduction to CMOS VLSI Design

Module-3 (MOS designs,Stick Diagrams,Designrules)

Lecture 1: Introduction

Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Systems Lecture # 10 MIPS Processor Example Material taken/adapted from.

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

Lecture 1: Circuits & Layout

Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 14: October 1, 2014 Layout and.

Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 5, 2011 Layout and.

EE4800 CMOS Digital IC Design & Analysis

Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.

VLSI Design Lecture 4-b: Layout Extraction Mohammad Arjomand CE Department Sharif Univ. of Tech.

Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout.

Introduction EE1411 Design Rules. EE1412 3D Perspective Polysilicon Aluminum.

STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

Advanced VLSI Design Unit 04: Combinational and Sequential Circuits.

EE141 © Digital Integrated Circuits 2nd Devices 1 Goal of this lecture  Present understanding of device operation  nMOS/pMOS as switches  How to design.

CMOS Fabrication nMOS pMOS.

Lecture 2: MIPS Processor Example

STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

Purpose of design rules:

CMOS VLSI Design Circuits & Layout. CMOS VLSI DesignSlide 2 Outline  A Brief History  CMOS Gate Design  Pass Transistors  CMOS Latches & Flip-Flops.

1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.

CMOS VLSI Design Introduction

CMOS VLSI Design MIPS Processor Example

Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 LECTURE 9: KEEE 4425 WEEK 7 CMOS LAYOUT AND STICK DIAGRAM (Cont’d)

CMOS VLSI Fabrication.

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-1 Panorama of VLSI Design Fabrication (Chem, physics) Technology (EE) Systems (CS) Matel.

STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 3, 2012 Layout and.

CMOS FABRICATION.

Introduction to CMOS VLSI Design Lecture 1: History & Layout Salman Zaffar Iqra University, Karachi Campus Spring 2012 Slides from D. Harris, Harvey Mudd.

EE141 Manufacturing 1 Chapter 2 Manufacturing Process and CMOS Circuit Layout 1 st rev. : March 7, nd rev. : April 10, 2003.

Stick Diagrams Stick Diagrams electronics.

CSE477 L06 Static CMOS Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 06: Static CMOS Logic Mary Jane Irwin (

2007/11/20 Paul C.-P. Chao Optoelectronic System and Control Lab., EE, NCTU P1 Copyright 2015 by Paul Chao, NCTU VLSI Lecture 0: Introduction Paul C.–P.

Lecture 1: Circuits and Layout National Chiao Tung University

Cell Design Standard Cells Datapath Cells General purpose logic

CMOS VLSI Design Lecture 2: Fabrication & Layout

2. Circuits & Layout. Diseño de Circuitos Digitales para Comunicaciones Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops.

Layout of CMOS Circuits

STICK Diagrams UNIT III : VLSI CIRCUIT DESIGN PROCESSES VLSI DESIGN

VLSI Design CMOS Layout

Where are we? Lots of Layout issues Line of diffusion style

ECE 424 – Introduction to VLSI Design

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example

Chapter 6 (I) CMOS Layout of Complexe Gate

Presentation transcript:

Introduction to CMOS VLSI Design Lecture 2: Standard Cell Design Layout Salman Zaffar IqraUniversity, Spring 2012 Slides from D. Harris, Harvey Mudd College USA

Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts Lecture 2

Example: Inverter Lecture 2

Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l Lecture 2

Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers Lecture 2

Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track Lecture 2

Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track Lecture 2

Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in l Lecture 2

Example: O3AI Sketch a stick diagram for O3AI and estimate area Lecture 2

Example: O3AI Sketch a stick diagram for O3AI and estimate area Lecture 2

Example: O3AI Sketch a stick diagram for O3AI and estimate area Lecture 2

Standard Cells Uniform cell height Uniform well height M1 VDD and GND rails M2 Access to I/Os Well / substrate taps Exploits regularity Lecture 2

Layout through Synthesis Synthesize HDL into gate-level netlist Place & Route using standard cell library Lecture 2