Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 7 Microsequencer Control Unit Design.

Slides:

Advertisements

Similar presentations

Control Unit Implemntation

Advertisements

CHAPTER 16 MICROPROGRAMMED CONTROL DR. H. WATSON FRANCISCO VASQUEZ

CS1104: Computer Organisation School of Computing National University of Singapore.

Chapter 7: Microprogrammed Control

PART 5: (2/2) Processor Internals CHAPTER 15: CONTROL UNIT OPERATION 1.

1 ITCS 3181 Logic and Computer Systems 2014 B. Wilkinson Slides8.ppt Modification date: Nov 3, 2014 Random Logic Approach The approach described so far.

UNIT-III CONTROL UNIT DESIGN

Chapter 16 Control Unit Operation No HW problems on this chapter. It is important to understand this material on the architecture of computer control units,

CS364 CH17 Micro-programmed Control

Chapter 16 Control Unit Implemntation. A Basic Computer Model.

Chapter 15 IA 64 Architecture Review Predication Predication Registers Speculation Control Data Software Pipelining Prolog, Kernel, & Epilog phases Automatic.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 6 CPU Design.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 5 Register Transfer Languages.

S. Barua – CPSC 440 CHAPTER 5 THE PROCESSOR: DATAPATH AND CONTROL Goals – Understand how the various.

Computer Organization and Architecture

Micro-operations Are the functional, or atomic, operations of a processor. A single micro-operation generally involves a transfer between registers, transfer.

Lecture 8 Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU.

Lecture 16 Today’s topics: –MARIE Instruction Decoding and Control –Hardwired control –Micro-programmed control 1.

Introduction to Computer Organization and Architecture Micro Program ภาษาเครื่อง ไมโครโปรแกรม.

CPU Design. Introduction – The CPU must perform three main tasks: Communication with memory – Fetching Instructions – Fetching and storing data Interpretation.

Florida International University Chapter 17 Micro-programmed Control Molina, Francisco Pineiro, Michael Romero, Rubymir.

1 Microprogrammed Control Computer Organization Prof. H. Yoon MICROPROGRAMMED CONTROL Control Memory Sequencing Microinstructions Microprogram Example.

MICROPROGRAMMED CONTROL

CONTROL UNIT OPERATION MICROPROGRAMMED CONTROL. 2.

Dr Mohamed Menacer College of Computer Science and Engineering Taibah University CE-321: Computer.

Microprogrammed Control Unit Control Memory Sequencing Microinstructions Microprogram Example Design of Control Unit Microinstruction Format.

Instructor: Yuzhuang Hu Midterm The midterm is schedule on June 17 th, 17:30-19:30 pm. It covers the following:  VHDL Programming. 

Chapter 6 CPU Design. 6.1 Specifying a CPU A CPU performs the following sequences of operations (Figure 6.1) –Fetch cycle –Decode cycle –Execute cycle.

Chapter 16 Micro-programmed Control

MICROPROGRAMMED CONTROL CH 17 Team # 2 Members: Wilmer Saint-Hilaire Alberto Mollinedo Vinicius Schuina Luis Perez.

Microprogrammed Control Chapter11:. Two methods for generating the control signals are: 1)Hardwired control o Sequential logic circuit that generates.

5-1 Chapter 5—Processor Design—Advanced Topics Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan Chapter.

PART 6: (1/2) Enhancing CPU Performance CHAPTER 16: MICROPROGRAMMED CONTROL 1.

Lecture 11 ALU and Control Unit Design Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU.

Lecture 15 Microarchitecture Level: Level 1. Microarchitecture Level The level above digital logic level. Job: to implement the ISA level above it. The.

Ch. 10 Central Processing Unit Designs - CISC. Two CPU designs CISC –Non-pipelined datapath with a microprogrammed control unit RISC –Pipelined datapath.

Basic Elements of Processor ALU Registers Internal data pahs External data paths Control Unit.

MICROPROGRAMMED CONTROL

GROUP 2 CHAPTER 16 CONTROL UNIT Group Members ๏ Evelio L. Hernandez ๏ Ashwin Soerdien ๏ Andrew Keiper ๏ Hermes Andino.

Chapter 7 Microsequencer Control Unit Design.

Types of Micro-operation  Transfer data between registers  Transfer data from register to external  Transfer data from external to register  Perform.

Basic Concepts Microinstructions The control unit seems a reasonably simple device. Nevertheless, to implement a control unit as an interconnection of.

Design a MIPS Processor (II)

Controller Implementation

Computer Organization and Architecture + Networks

Micro-programmed Control

Cpe 252: Computer Organization1 Dr. Lo’ai Tawalbeh Chapter 7: Microprogrammed Control.

Overview Control Memory Comparison of Implementations

Micro-programmed Control Unit

MICROPROGRAMMED CONTROL

INDEX UNIT-III PPT SLIDES

Processor: Finite State Machine & Microprogramming

Computer Organization and Design

Controller Implementation--Part II

Control Unit Introduction Types Comparison Control Memory

Processor Organization and Architecture

MICROPROGRAMMED CONTROL

William Stallings Computer Organization and Architecture 8th Edition

Computer Architecture

MICROPROGRAMMED CONTROL

MICROPROGRAMMED CONTROL

William Stallings Computer Organization and Architecture

Chapter 7 Microprogrammed Control

UNIT – III Microprogrammed Control

Presentation transcript:

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 7 Microsequencer Control Unit Design

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline Basic Microsequencer DesignBasic Microsequencer Design Very Simple MicrosequencerVery Simple Microsequencer Relatively Simple MicrosequencerRelatively Simple Microsequencer Reducing the Number of MicroinstructionsReducing the Number of Microinstructions Microcoded vs. Hardwired ControlMicrocoded vs. Hardwired Control Pentium MicroprocessorPentium Microprocessor

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-stuff Micro-operationsMicro-operations MicroinstructionsMicroinstructions MicroprogramsMicroprograms

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Microsequencer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generating the Next Address Current Address + 1Current Address + 1 Address specified by microinstructionAddress specified by microinstruction Microsubroutine registerMicrosubroutine register Mapping hardwareMapping hardware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microinstruction Format

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Microcode HorizontalHorizontal VerticalVertical DirectDirect

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 A Very Simple Microsequencer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Mapping Logic

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 State Addresses StateAddress FETCH (0) FETCH (1) FETCH (2) ADD (8) ADD (9) AND (10) AND (11) JMP (12) INC (14)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Partial Microcode StateAddressSELADDR FETCH (0) FETCH (1) FETCH (2) 1XXXX ADD (8) ADD (9) AND (10) AND (11) JMP (12) INC (14) 00000

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operations MnemonicMicro-Operation ARPC AR  PC ARDR AR  DR[5..0] PCIN PC  PC + 1 PCDR PC  DR[5..0] DRM DR  M IRDR IR  DR[7..6] PLUS AC  AC + DR AND AC  AC^DR ACIN AC  AC + 1

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Horizontal Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimized Horizontal Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Generic Vertical Microcode Decoding

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields Include a NOP in each fieldInclude a NOP in each field

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields Include a NOP in each fieldInclude a NOP in each field Distribute remaining micro-operations to minimize total number of bits requiredDistribute remaining micro-operations to minimize total number of bits required

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Field Assignments Simultaneous micro-operations in different fieldsSimultaneous micro-operations in different fields Include a NOP in each fieldInclude a NOP in each field Distribute remaining micro-operations to minimize total number of bits requiredDistribute remaining micro-operations to minimize total number of bits required Group together micro-operations that modify the same registerGroup together micro-operations that modify the same register

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments M1M2 NOPNOP DRMPCIN

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments M1M2 NOPNOP DRMPCIN ACINPCDR PLUSARPC ANDAIDR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments M1M2 NOPNOP DRMPCIN ACINPCDR PLUSARPC ANDAIDR

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Assignments and Field Values

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Vertical Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operation Generation

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Nanoinstructions

Directly Generating Control Signals Output control signals instead of micro- operationsOutput control signals instead of micro- operations No external decoding requiredNo external decoding required No external hardware required to generate control signalsNo external hardware required to generate control signals More difficult to codeMore difficult to code

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Preliminary Direct Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Optimize Direct Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Relatively Simple Microsequencer No changes toNo changes to –Instruction set –Data paths –ALU

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Modified State Diagram

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microsequencer Hardware

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 State Assignments

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Condition Values

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Branch Types

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Branch Logic

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Partial Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Partial Microcode (continued)

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Micro-operations

Horizontal Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Horizontal Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Horizontal Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Control Signals

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Reducing the Number of Microinstructions MicrosubroutinesMicrosubroutines Microcode JumpsMicrocode Jumps

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microsubroutines

Revised State Assignments

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microsequencer with Microsubroutines

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Branch Types

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Branch Logic

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microcode Jumps

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Revised Microcode

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microprogrammed Control vs. Hardwired Control Complexity of the instruction setComplexity of the instruction set

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microprogrammed Control vs. Hardwired Control Complexity of the instruction setComplexity of the instruction set Ease of modificationEase of modification

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Microprogrammed Control vs. Hardwired Control Complexity of the instruction setComplexity of the instruction set Ease of modificationEase of modification Clock speedClock speed

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 The Pentium Microprocessor

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Basic Microsequencer DesignBasic Microsequencer Design Very Simple MicrosequencerVery Simple Microsequencer Relatively Simple MicrosequencerRelatively Simple Microsequencer Reducing the Number of MicroinstructionsReducing the Number of Microinstructions Microcoded vs. Hardwired ControlMicrocoded vs. Hardwired Control Pentium MicroprocessorPentium Microprocessor