Direct Map Cache Tracing Exercise. Exercise #1: Setup Information CS2100 Cache I 2 Memory 4GB Memory Address 310N-1N Block Number Offset 1 Block = 8 bytes.

Slides:

Advertisements

Similar presentations

Cache Memory Exercises. Questions I Given: –memory is little-endian and byte addressable; memory size; –number of cache blocks, size of cache block –An.

Advertisements

CS2100 Computer Organisation Cache II (AY2014/2015) Semester 2.

1 Memory Systems Virtual Memory Lecture 25 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007.

Homework 2 Review Cornell CS Calling Conventions int gcd(int x, int y) { int t, a = x, b = y; while(b != 0) { t = b; b = mod(a, b); a = t; } return.

The Lord of the Cache Project 3. Caches Three common cache designs: Direct-Mapped store in exactly one cache line Fully Associative store in any cache.

Computer ArchitectureFall 2007 © November 14th, 2007 Majd F. Sakr CS-447– Computer Architecture.

How caches take advantage of Temporal locality

Memory Hierarchies Exercises [ ] Describe the general characteristics of a program that would exhibit very little spatial or temporal locality with.

Virtual Memory. Why do we need VM? Program address space: 0 – 2^32 bytes –4GB of space Physical memory available –256MB or so Multiprogramming systems.

Caches The principle that states that if data is used, its neighbor will likely be used soon.

Cache Organization Topics Background Simple examples.

CDA 3103 Computer Organization Review Instructor: Hao Zheng Dept. Comp. Sci & Eng. USF.

©UCB CS 161 Ch 7: Memory Hierarchy LECTURE 24 Instructor: L.N. Bhuyan

CSCE 212 Quiz 11 – 4/13/11 Given a direct-mapped cache with 8 one-word blocks and the following 32-bit memory address references: 1 2, ,

Caches – basic idea Small, fast memory Stores frequently-accessed blocks of memory. When it fills up, discard some blocks and replace them with others.

MPC 555 Memory Controller and Chip Select

Caches Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H 5.1, 5.2 (except writes)

Caches – basic idea Small, fast memory Stores frequently-accessed blocks of memory. When it fills up, discard some blocks and replace them with others.

Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system?

Virtual Memory CS Introduction to Operating Systems.

Ch. 12 Cache Direct Mapped Cache. Comp Sci mem hierarchy 2 Memory Hierarchy Registers: very few, very fast cache memory: small, fast main memory:

1 CMPE 421 Advanced Computer Architecture Accessing a Cache PART1.

ACOE2011 Cache memory Homework – Q1 A computer has a 32 bit address and a 64 bit data bus with address resolution to the byte level. The computer is using.

Chapter 91 Logical Address in Paging  Page size always chosen as a power of 2.  Example: if 16 bit addresses are used and page size = 1K, we need 10.

CS2100 Computer Organisation Cache II (AY2015/6) Semester 1.

Lecture Objectives: 1)Explain the relationship between miss rate and block size in a cache. 2)Construct a flowchart explaining how a cache miss is handled.

DECStation 3100 Block Instruction Data Effective Program Size Miss Rate Miss Rate Miss Rate 1 6.1% 2.1% 5.4% 4 2.0% 1.7% 1.9% 1 1.2% 1.3% 1.2% 4 0.3%

11 Intro to cache memory Kosarev Nikolay MIPT Nov, 2009.

Systems I Cache Organization

CS2100 Computer Organisation Cache I (AY2015/6) Semester 1.

Additional Slides By Professor Mary Jane Irwin Pennsylvania State University Group 1.

Cache Operation.

Cache Organization 1 Computer Organization II © CS:APP & McQuain Cache Memory and Performance Many of the following slides are taken with.

CSE 351 Caches. Section Feedback Before we begin, we’d like to get some feedback about section If you could answer the following questions on the provided.

COSC2410: LAB 19 INTRODUCTION TO MEMORY/CACHE DIRECT MAPPING 1.

CS2100 Computer Organisation Cache I (AY2010/2011) Semester 2.

Main Memory: Paging and Segmentation CSSE 332 Operating Systems Rose-Hulman Institute of Technology.

Презентацию подготовила Хайруллина Ч.А. Муслюмовская гимназия Подготовка к части С ЕГЭ.

CSCI206 - Computer Organization & Programming

Address – 32 bits WRITE Write Cache Write Main Byte Offset Tag Index Valid Tag Data 16K entries 16.

Tutorial Nine Cache CompSci Semester One 2016.

CS2100 Computer Organization

Direct Cache Structure

Replacement Policy Replacement policy:

Sarah Diesburg Operating Systems CS 3430

Consider a Direct Mapped Cache with 4 word blocks

Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system?

Notation Addresses are ordered triples:

Exploiting Memory Hierarchy Chapter 7

CSCI206 - Computer Organization & Programming

Lecture 21: Memory Hierarchy

Lecture 21: Memory Hierarchy

CSCI206 - Computer Organization & Programming

FIGURE 12-1 Memory Hierarchy

Sarah Diesburg Operating Systems CS 3430

Interconnect with Cache Coherency Manager

Lecture 22: Cache Hierarchies, Memory

Help! How does cache work?

Direct Mapping.

Module IV Memory Organization.

Chap. 12 Memory Organization

Basic Cache Operation Prof. Eric Rotenberg

Lecture 21: Memory Hierarchy

Sarah Diesburg Operating Systems CS 3430

Cache Memory and Performance

Lecture 13: Cache Basics Topics: terminology, cache organization (Sections )

Sarah Diesburg Operating Systems CS 3430

Overview Problem Solution CPU vs Memory performance imbalance

Memory Management & Virtual Memory

Presentation transcript:

Direct Map Cache Tracing Exercise

Exercise #1: Setup Information CS2100 Cache I 2 Memory 4GB Memory Address 310N-1N Block Number Offset 1 Block = 8 bytes Cache 32Bytes 1 Block = 8 bytes N+M-1 310N-1N Tag Offset Index Offset, N = Block Number = Number of Cache Blocks = Cache Index, M = Cache Tag =

Exercise #2: Tracing Memory Access Using the given setup, trace the following memory loads:  Load from addresses: 4, 0, 8, 12, 36, 0, 4 Note that “A”, “B”…. “J” represents word-size data CS2100 Cache I 3 Memory Content Address Data 0 A 4 B 8 C 12 D … … 32 I 36 J … …

CS2100 Exercise #2: Load #1  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 4 = IndexValidTagWord0Word TagOffset 00 Index Cache I 4

CS2100 Exercise #2: Load #2  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 0 = IndexValidTagWord0Word TagOffset 00 Index Cache I 5

CS2100 Exercise #2: Load #3  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 8 = IndexValidTagWord0Word TagOffset 01 Index Cache I 6

CS2100 Exercise #2: Load #4  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 12 = IndexValidTagWord0Word TagOffset 01 Index Cache I 7

CS2100 Exercise #2: Load #5  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 36 = IndexValidTagWord0Word TagOffset 00 Index Cache I 8

CS2100 Exercise #2: Load #6  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 0 = IndexValidTagWord0Word TagOffset 00 Index Cache I 9

CS2100 Exercise #2: Load #7  Addresses: 4, 0, 8, 12, 36, 0, 4 Address 4 = IndexValidTagWord0Word TagOffset 00 Index Cache I 10