Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits

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Presentation transcript:

Introduction to CMOS VLSI Design Lecture 10: Sequential Circuits David Harris Harvey Mudd College Spring 2004

Outline Floorplanning Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking 10: Sequential Circuits

Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline 10: Sequential Circuits

Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high Delay fast tokens so they don’t catch slow ones. 10: Sequential Circuits

Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 10: Sequential Circuits

Pipelining 10: Sequential Circuits

Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches 10: Sequential Circuits

Timing Diagrams Contamination and Propagation Delays tpd tcd tpcq tccq Logic Prop. Delay tcd Logic Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tccq Latch/Flop Clk-Q Cont. Delay tpdq Latch D-Q Prop Delay tcdq Latch D-Q Cont. Delay tsetup Latch/Flop Setup Time thold Latch/Flop Hold Time 10: Sequential Circuits

Max-Delay: Flip-Flops 10: Sequential Circuits

Max-Delay: Flip-Flops 10: Sequential Circuits

Min-Delay: Flip-Flops 10: Sequential Circuits

Min-Delay: Flip-Flops 10: Sequential Circuits

Positive Skew & Negative Skew PS Clk & Data Same Direction NS Clk & Data Difft Direction 10: Sequential Circuits

Skew: Flip-Flops 10: Sequential Circuits

Skew: Flip-Flops 10: Sequential Circuits

Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks Very slow – nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 10: Sequential Circuits

Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk 10: Sequential Circuits