Sarah Diesburg Operating Systems CS 3430 Suggested Exercise #7 Sarah Diesburg Operating Systems CS 3430

Problem 1 (a) 32-bit addressing Page size: 4 Kbytes (212 bytes) Pure paging 232 bytes / 212 bytes/entry= 220 entries Each page table entry 20-bit physical page number 4 status bits Page table size = 220 entries * 3 bytes/entry = 3 Mbytes

Paging Diagram 32 – 12 = 20 bits for 32-bit machines log2(4KB) = 12 bits for 4-KB pages Virtual page number Offset Page table size > Error 4 status bits 220 entries Physical page number Physical page number Offset

Problem 1 (b) Segmented-paging address translation Page size: 4 Kbytes (212 bytes) Offset: 12 bits Three segments: code, data, stack Virtual segment number: log23 = 2 bits Virtual page number 32 – 12 – 2 = 18 bits

Segmented Paging 32 bits for 4-GB 32 - 2 - 12 = 18 bits Page table base Page table bound 22 entries 12 bits for 4-KB pages 20 bits num of entries defined by bound; up to 218 Seg # Offset Virt page # Phy page # log2(3 segments) = 2 bits

Segmented Paging 32 – 2 – 12 = 18 bits 218 Seg # Offset Virt page # Page table size > Error Page table base + Phy page # Phy page # Offset log2(4GB) = 32 bits

Problem 1 (b) Each segment (code, data, stack) uses 16 Kbytes = 4 pages 3 page tables: Code-segment page table: 4 entries Page table entry 20 bits to address all physical page numbers 4 status bits 24 bits/entry * 4 entries = 96 bits Same for data-segment page table and stack-segment page table Total: 96 bits * 3 = 288 bits

Problem 1 (b) Each segment (code, data, stack) uses 16 Kbytes = 4 pages 1 segment table: 4 entries 32 bits for the page table base 18 bits for the page table number bound 4 status bits Total memory: 4 * (32 + 18 + 4) = 216 bits

Problem 2 Effective access time Cache hit rate L1 cache 1 clock cycle 98% L2 cache 2 clock cycles 99% Memory 6 clock cycles 100% Effective access time = P(hit)*cost(hit) + P(miss)*cost(miss) = P(L1 hit)*cost(L1 hit) + P(L1 miss)*cost(L1 miss) = 98%*(1 clock cycle) + 2%*cost(L1_miss)

Problem 2 What is cost(L1_miss)? cost(L1_miss) = P(L2_hit)*cost(L1_miss+L2_hit) + P(L2_miss)*cost(L1_miss+L2_miss+mem_hit) Access time Cache hit rate L1 cache 1 clock cycle 98% L2 cache 2 clock cycles 99% Memory 6 clock cycles 100%

Problem 2 Access time Cache hit rate L1 cache 1 clock cycle 98% 2 clock cycles 99% Memory 6 clock cycles 100% L1 98% 1 cycle 1% 1 cycle hit L2 99% 2 cycles 1% 2 cycles hit memory 100% 6 cycles hit

Problem 2 Effective access time = 98%*1 + 2%*99%(1 + 2) + 2%*1%(1 + 2 + 6) L1 98% 1 cycle 2% 1 cycle hit L2 99% 2 cycles 1% 2 cycles hit memory 100% 6 cycles hit