Systems for Nuclear Physics Today 1.Number of Channels Approx. 1,000 2.Short & Reconfigurable Experimental Setups with variety of Detector Types 3.Human & Financial Resources Low Systems for Nuclear Physics Tomorrow 1.Number of Channels Approx. 20,000 2.Short & Reconfigurable …. 3.Human &... Measure 1.TPC, Si, CsI … (E & T via Charge Sampling), 2.Efficient Trigger events/sec (TPC like) Systems for Nuclear Physics Today 1.Number of Channels Approx. 1,000 2.Short & Reconfigurable Experimental Setups with variety of Detector Types 3.Human & Financial Resources Low Systems for Nuclear Physics Tomorrow 1.Number of Channels Approx. 20,000 2.Short & Reconfigurable …. 3.Human &... Measure 1.TPC, Si, CsI … (E & T via Charge Sampling), 2.Efficient Trigger events/sec (TPC like)

Bragg trace measure

Projects employing GET ACTAR ( GANIL, IRFU, IPNO, SFTC, …) – Micromegas + Si – 20k channels 2p-TPC (CENBG) – GEM/Micromegas – 20k channels AT-TPC (MSU, LBL …) – Micromegas – 12k channels GASPARD (GANIL, IRFU, IPNO,... ) – Si & CsI – 15k channels BTD (IRFU & GANIL) – 100 channels SAMÜRAI-TPC (RIKEN) – Micromegas -15k channels FORFIRE – IRFU – Industry Test system - IRFU Under Study use of GET/ GET modules S3 – (SPIRAL2+IRFI+…) – Si/gas tracker channels MINOS  (p;2p,  ) - (IRFU)– Micromegas - 8K channels FIDIAS (IRFU) – Micromegas 5K Channels (IRFU) Projects employing GET ACTAR ( GANIL, IRFU, IPNO, SFTC, …) – Micromegas + Si – 20k channels 2p-TPC (CENBG) – GEM/Micromegas – 20k channels AT-TPC (MSU, LBL …) – Micromegas – 12k channels GASPARD (GANIL, IRFU, IPNO,... ) – Si & CsI – 15k channels BTD (IRFU & GANIL) – 100 channels SAMÜRAI-TPC (RIKEN) – Micromegas -15k channels FORFIRE – IRFU – Industry Test system - IRFU Under Study use of GET/ GET modules S3 – (SPIRAL2+IRFI+…) – Si/gas tracker channels MINOS  (p;2p,  ) - (IRFU)– Micromegas - 8K channels FIDIAS (IRFU) – Micromegas 5K Channels (IRFU)

Con. Design ASIC 1 Sys. Proto 1 Sys. Proto 2 ASIC 2 Production Cards Beam Test R&D Financed 75% (France) 25% (US) R&D Financed 75% (France) 25% (US)

PAC Very FE Pre-amp/ Protection Very FE Pre-amp/ Protection 3 Levels Trigger Clock 3 Levels Trigger Clock Front-End Stab./Security Coding Front-End Stab./Security Coding FARM L-3 Event- Building Data Control S. Control Web Services Security FARM L-3 Event- Building Data Control S. Control Web Services Security

ZAP-PAC

CMOS 0.35µm Int./Ext. PAC &/or Filter Gain & Disc/channel  120, 240 fC, 1, 10 pC. Shaping nsec Sampling rate 1-100Mhz  25MHz ADC 12/14bits Selective Readout – Hit Reg. Windowed SCA readout  128/256/512 or variable 2 fast time- consequative SCA windows Pulser facilities Spy CMOS 0.35µm Int./Ext. PAC &/or Filter Gain & Disc/channel  120, 240 fC, 1, 10 pC. Shaping nsec Sampling rate 1-100Mhz  25MHz ADC 12/14bits Selective Readout – Hit Reg. Windowed SCA readout  128/256/512 or variable 2 fast time- consequative SCA windows Pulser facilities Spy Filter DISC HIT Reg. HIT Reg. ADC Pulser X64 Or X64 Or X64 Mulx A na. Mem. CoBo Trigger c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Filter PAC c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Generic

11 Some numbers: Simulation results Charge resolution: versus input capacitor and peaking time

Cooling Study CEM Study Power Supplies Study

1GBit X10 CoBo 1GBit X10 CoBo 10 Gbit 10 3 Hz 1.2GBit X4 AsAd 1.2GBit X4 AsAd BuTiS/GTS/ Centrum/ …

Nucl. Phys. Have Limited Experience  Scenarios/Simul. 4-level triggers 4-level triggers L0: External trigger L1: Time dependent Multip. trigger  Self Trigger, …  Self Trigger, … L2: Hit Pattern trigger  Self Trigger, calculated read pattern … read pattern … L3: Soft trigger L3: Soft trigger Compute the digital trigger from CoBos (25MHz) Compute the digital trigger from CoBos (25MHz) Time stamp (48b, 10ns) and event N° (32b) Time stamp (48b, 10ns) and event N° (32b) Distribute the 100MHz clock for the synchronisation Distribute the 100MHz clock for the synchronisation Nucl. Phys. Have Limited Experience  Scenarios/Simul. 4-level triggers 4-level triggers L0: External trigger L1: Time dependent Multip. trigger  Self Trigger, …  Self Trigger, … L2: Hit Pattern trigger  Self Trigger, calculated read pattern … read pattern … L3: Soft trigger L3: Soft trigger Compute the digital trigger from CoBos (25MHz) Compute the digital trigger from CoBos (25MHz) Time stamp (48b, 10ns) and event N° (32b) Time stamp (48b, 10ns) and event N° (32b) Distribute the 100MHz clock for the synchronisation Distribute the 100MHz clock for the synchronisation MTH MTL Number Of Buckets: NOB_H Number Of Buckets: NOB_L ADC Mulx CoBo Trigger HIT Reg. HIT Reg. ASIC-AGET Trigger Building Data Transfer

Shebli ANVAR, CEA Irfu Global Network Data Server Offline Analysis External Systems Control & Monitoring FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip Ethernet 10 Gb Network Switch FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip FPGA Embedded Processor RAM Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip Computer Farm Point-to-point CoBo

S. Anvar, GET coll. Multi-Platform framework Fully Object Oriented Client-Server design architecture. Fully Object Oriented Client-Server design architecture. ICE & SOAP middleware. ICE & SOAP middleware. Evolutive Data Formats. Evolutive Data Formats. Software Debbuging/Simul. Tools. Software Debbuging/Simul. Tools. NARVAL for data management NARVAL for data management (– ADA, TCP/IP). Multi-Platform framework Fully Object Oriented Client-Server design architecture. Fully Object Oriented Client-Server design architecture. ICE & SOAP middleware. ICE & SOAP middleware. Evolutive Data Formats. Evolutive Data Formats. Software Debbuging/Simul. Tools. Software Debbuging/Simul. Tools. NARVAL for data management NARVAL for data management (– ADA, TCP/IP).

Genericity  Multi-Platform (Linux, VxWorks, Windows, Mac) framework Fully Object Oriented Client-Server design architecture. ICE & SOAP middleware. Evolutive Data Formats. Software Développement /Debbuging/Simulation Tools. NARVAL for data management (NARVAL – ADA, TCP/IP).

Shebli ANVAR, CEA Irfu Offline Processing StorageStorage Online Processing Readout & formatting Digitization Detection Channel Configuration and Control MonitoringMonitoring Buffering & Routing Hardware Firmware Software

Embedded Implementation (Upstream) Shebli ANVAR, CEA Irfu FPGA Embedded Processor RAM Ethernet 100 Control (I2C, etc.) Ethernet 1000 Memory bus System on Chip Digitization Digitization (ASIC+ADC+…) Allows use of standard multi-Gb switches for data concentration and routing

– 32, Channel Number – can be increased TRIG

ZAP Ext preamp Ext preamp AGET ADC ASAD Readout Signal process Gb transfer Clock distrib Trigger L0-2 Trigger L0-2 Process L1 -> L2 Process L1 -> L2 CoBo MUTANT DAQ Config Configmanager managerECCECC DatabaseDatabase SLOWCONTROL ClockproviderClockprovider Time reference (GSI Butis) Spy box boxSpy Inspection box time alignment (Riken) Front-end boards Asic+ADC HV, I, T monitoring Front-end boards Asic+ADC HV, I, T monitoring Data Readout & Trig Zero suppress Time stamp 3-Level trigger Data Readout & Trig Zero suppress Time stamp 3-Level trigger DAQ & Slow control Run control Online analysis Electronics control DAQ & Slow control Run control Online analysis Electronics control EventbuilderEventbuilder EventanalysisEventanalysis RuncontrolRuncontrol StorageStorage NARVAL GET Overview Micro-TCA standard