ICS 252 Introduction to Computer Design Multi-level Logic Optimization Fall 2006 Eli Bozorgzadeh Computer Science Department-UCI.

Slides:



Advertisements
Similar presentations
ENGG3190 Logic Synthesis “Multi Level Logic” (Part II) Winter 2014 S. Areibi School of Engineering University of Guelph.
Advertisements

The BDS Circuit Synthesis System What it Does and Doesn’t Do.
FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n Logic synthesis. n Placement and routing.
Winter 2005ICS 252-Intro to Computer Design ICS 252 Introduction to Computer Design Lecture 5-Scheudling Algorithms Winter 2005 Eli Bozorgzadeh Computer.
ENGG3190 Logic Synthesis “Multi Level Logic” (Part I) Winter 2014 S. Areibi School of Engineering University of Guelph.
ECE Synthesis & Verification 1 ECE 667 Spring 2011 ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits Introduction to Logic Synthesis.
ECE 667 Synthesis and Verification of Digital Systems
ECE Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Introduction.
Logic Synthesis Part II
Reducing Multi-Valued Algebraic Operations to Binary J.-H. Roland Jiang Alan Mishchenko Robert K. Brayton Dept. of EECS University of California, Berkeley.
Technology Mapping.
1 Generalized Buffering of PTL Logic Stages using Boolean Division and Don’t Cares Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering,
Logic Synthesis Outline –Logic Synthesis Problem –Logic Specification –Two-Level Logic Optimization Goal –Understand logic synthesis problem –Understand.
Logic Synthesis 1 Outline –Logic Synthesis Problem –Logic Specification –Two-Level Logic Optimization Goal –Understand logic synthesis problem –Understand.
DAG-Aware AIG Rewriting Alan Mishchenko, Satrajit Chatterjee, Robert Brayton Department of EECS, University of California Berkeley Presented by Rozana.
COE 561 Digital System Design & Synthesis Sequential Logic Synthesis Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum.
ICS 252 Introduction to Computer Design
Logic Decomposition ECE1769 Jianwen Zhu (Courtesy Dennis Wu)
Overview Part 2 – Circuit Optimization 2-4 Two-Level Optimization
B-1 Appendix B - Reduction of Digital Logic Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles.
Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 9 – Multilevel Optimization.
Department of Computer Engineering
Boolean Methods for Multi-level Logic Synthesis Giovanni De Micheli Integrated Systems Centre EPF Lausanne This presentation can be used for non-commercial.
Electrical and Computer Engineering Archana Rengaraj ABC Logic Synthesis basics ECE 667 Synthesis and Verification of Digital Systems Spring 2011.
State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect19: Multi Level Logic Minimization.
Computer-Aided Design of Digital VLSI Circuits & Systems Priyank Kalla Dept. of Elec. & Comp. Engineering University of Utah,SLC Perspectives on Next-Generation.
40551 Logic Synthesis Optimization Dr. Yaser M. Agami Khalifa Fall 2004 Lecture # 1.
Zvi Kohavi and Niraj K. Jha 1 Multi-level Logic Synthesis.
1 Multi-Level Logic Synthesis Slides courtesy of Andreas Kuehlmann (Cadence)
Optimization Algorithm
1 EECS 219B Spring 2001 Timing Optimization Andreas Kuehlmann.
Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Combinational network delay. n Logic optimization.
ICS 252 Introduction to Computer Design Lecture 9 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
Two Level and Multi level Minimization
Elements of discrete devices synthesis (module T170M012) 2012 Kaunas university of technology Electronic and measurement systems dep. Doc. dr. Žilvinas.
COE 561 Digital System Design & Synthesis Multiple-Level Logic Synthesis Dr. Muhammad E. Elrabaa Computer Engineering Department King Fahd University of.
ICS 252 Introduction to Computer Design Lecture 10 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 4: Logic Optimization Chapter 4.
Logic Functions: XOR, XNOR
ICS 252 Introduction to Computer Design Lecture 12 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
Technology Mapping. 2 Technology mapping is the phase of logic synthesis when gates are selected from a technology library to implement the circuit. Technology.
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Multi-Level Logic Synthesis.
Ch.5 Logic Design Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology 1.
Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Combinational network delay. n Logic optimization.
Output Grouping-Based Decomposition of Logic Functions Petr Fišer, Hana Kubátová Department of Computer Science and Engineering Czech Technical University.
1 Timing Closure and the constant delay paradigm Problem: (timing closure problem) It has been difficult to get a circuit that meets delay requirements.
2009/6/30 CAV Quantifier Elimination via Functional Composition Jie-Hong Roland Jiang Dept. of Electrical Eng. / Grad. Inst. of Electronics Eng.
ICS 252 Introduction to Computer Design Lecture 8- Heuristics for Two-level Logic Synthesis Winter 2005 Eli Bozorgzadeh Computer Science Department-UCI.
ICS 252 Introduction to Computer Design Lecture 8 Winter 2004 Eli Bozorgzadeh Computer Science Department-UCI.
State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect18: Multi Level Logic Minimization.
Lecture 1 Gunjeet kaur Dronacharya group of institutions.
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design
Finite state machine optimization
Finite state machine optimization
Chapter 4 Simplification of Boolean Functions Karnaugh Maps
Reconfigurable Computing
A Boolean Paradigm in Multi-Valued Logic Synthesis
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design
Topics Logic synthesis. Placement and routing..
332:437 Lecture 3 Hardware Design Methodology and Advanced Logic Design Hardware design.
Sungho Kang Yonsei University
ICS 252 Introduction to Computer Design
Technology Mapping I based on tree covering
VLSI CAD Flow: Logic Synthesis, Placement and Routing Lecture 5
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design
Illustrative Example p p Lookup Table for Digits of h g f e ) ( d c b
*Internal Synthesizer Flow *Details of Synthesis Steps
Presentation transcript:

ICS 252 Introduction to Computer Design Multi-level Logic Optimization Fall 2006 Eli Bozorgzadeh Computer Science Department-UCI

2 Fall 2007ICS 252-Intro to Computer Design Multi-level logic optimization Representation Optimization –Goal: area/delay –Algorithmic: algebraic, Boolean –Rule-based methods Examples of transformations

3 Fall 2007ICS 252-Intro to Computer Design Motivation Multiple-level networks: –Semi-custom libraries. –Gates versus macros (PLAs): – More flexibility. – Better performance. – Applicable to a variety of designs. ©GDM

4 Fall 2007ICS 252-Intro to Computer Design Circuit Modeling Logic network: –Interconnection of logic functions. –Hybrid structural/behavioral model. Bound (mapped) networks: –Interconnection of logic gates. –Structural model. ©GDM

5 Fall 2007ICS 252-Intro to Computer Design Multi-level vs. Two-level PLA –Control logic –Constrained layout –Highly automatic –Technology independent –Slower –Multi valued function –Input,output, state encoding Multi-level –All logic –General –Automatic –Partially tech dependent –Can be faster

6 Fall 2007ICS 252-Intro to Computer Design Example of bound network a b c x y va vb vc vp vq vx vy p q ©GDM

7 Fall 2007ICS 252-Intro to Computer Design Example of network ©GDM

8 Fall 2007ICS 252-Intro to Computer Design Example of network a b c d e v=a’d+bd+c’d+ae’ p=ce+de r=p+a’ s=r+b’ t=ac+bd+bc+bd+e q=a+b u=q’c+qc’+qc w x y z ©GDM

9 Fall 2007ICS 252-Intro to Computer Design Network optimization Minimize area (power) –Subject to delay constraint Minimize maximum delay –Subject to area (power) constraint Minimize power consumption –Subject to delay constraint Maximize testability ©GDM

10 Fall 2007ICS 252-Intro to Computer Design Estimation Area: –Number of literals –Number of functions/gates Delay –Number of stages –Refined gate delay models –paths ©GDM

11 Fall 2007ICS 252-Intro to Computer Design Problem analysis Multi-level optimization is hard Exact models –Exponential complexity –Impractical Approximate methods –Heuristics algorithms –Rule-based methods ©GDM

12 Fall 2007ICS 252-Intro to Computer Design Strategies for optimization Improve circuit step by step –Circuit transformation Preserve network behavior Methods differ in –Types of transformations –Selection and order of transformations ©GDM

13 Fall 2007ICS 252-Intro to Computer Design Eliminate Eliminate one function from the network Perform variable substitution Example: –s = r + b’; r = p + a’; –s = p + a’ + b’; ©GDM

14 Fall 2007ICS 252-Intro to Computer Design Example a b c d e v=a’d+bd+c’d+ae’ p=ce+de s=p+a’+b’ t=ac+bd+bc+bd+e q=a+b u=q’c+qc’+qc w x y z ©GDM

15 Fall 2007ICS 252-Intro to Computer Design decomposition Break one function into smaller ones Introduce new vertices in the network Example ©GDM

16 Fall 2007ICS 252-Intro to Computer Design Example a b c d e V=jd+ae’ p=ce+de r=p+a’ s=r+b’ t=ac+bd+bc+bd+e q=a+b u=q’c+qc’+qc w x y z v=a’+b+c’ ©GDM

17 Fall 2007ICS 252-Intro to Computer Design Example extraction Find a common sub-expression of two or more expressions Extract sub-expression as new function Introduce new vertex in the network Example ©GDM

18 Fall 2007ICS 252-Intro to Computer Design Example a b c d e v=a’d+bd+c’d+ae’ p=ke r=p+a’ s=r+b’ t=ka+kb+e q=a+b u=q’c+qc’+qc w x y z K=c+d ©GDM

19 Fall 2007ICS 252-Intro to Computer Design Simplification Simplify a local function Example ©GDM

20 Fall 2007ICS 252-Intro to Computer Design Example a b c d e v=a’d+bd+c’d+ae’ p=ce+de r=p+a’ s=r+b’ t=ac+bd+bc+bd+e q=a+b u=q+c w x y z ©GDM

21 Fall 2007ICS 252-Intro to Computer Design substitution Simplify a local function by using an additional input that was not previously in its support set. Example ©GDM

22 Fall 2007ICS 252-Intro to Computer Design Example a b c d e v=a’d+bd+c’d+ae’ p=ke r=p+a’ s=r+b’ t=ka+kb+e q=a+b u=q’c+qc’+qc w x y z K=c+d ©GDM

23 Fall 2007ICS 252-Intro to Computer Design Example a b c d e v=a’d+bd+c’d+ae’ p=ke r=p+a’ s=r+b’ t=kq+e q=a+b u=q’c+qc’+qc w x y z K=c+d ©GDM

24 Fall 2007ICS 252-Intro to Computer Design Optimization approaches Algorithmic approach –Define an algorithm for each transformation –Algorithm is an operator on the network Rule-based approach –Rule-data base Set of pattern pairs –Pattern replacement by rules ©GDM

25 Fall 2007ICS 252-Intro to Computer Design Algorithmic approach Each operator has well-defined properties –Heuristic methods –Weak optimality Sequence of operators –Defined by scripts in SIS –Based on experience ©GDM

26 Fall 2007ICS 252-Intro to Computer Design Example of script in SIS sweep; eliminate -1 simplify –m nocomp eliminate -1 sweep; eliminate 5 simplify –m nocomp resub –a fx resub –a;sweep… ©GDM

27 Fall 2007ICS 252-Intro to Computer Design Boolean and algebraic methods Boolean methods –Exploit properties of logic functions –Use don’t care conditions –Complex Algebraic methods –View functions as polynomials –Exploit properties of polynomial algebra –Simpler, faster but weaker ©GDM

28 Fall 2007ICS 252-Intro to Computer Design summary Multilevel logic synthesis is performed by step-wise transformations Algorithms are based on both the Boolean and the algebraic models Rule-based ©GDM