CS61C L20 Single Cycle Datapath, Control (1) Chae, Summer 2008 © UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #20 – Single Cycle CPU Datapath and Control

CS61C L20 Single Cycle Datapath, Control (2) Chae, Summer 2008 © UCB Review CPU design involves Datapath,Control Datapath in MIPS involves 5 CPU stages 1) Instruction Fetch 2) Instruction Decode & Register Read 3) ALU (Execute) 4) Memory 5) Register Write

CS61C L20 Single Cycle Datapath, Control (3) Chae, Summer 2008 © UCB Single Cycle CPU Single Cycle CPU: All stages of an instruction are completed within one long clock cycle. The clock cycle is made sufficient long to allow each instruction to complete all stages without interruption and within one cycle. For each instruction, how do we control the flow of information though the datapath? 1. Instruction Fetch 2. Decode/ Register Read 3. Execute4. Memory 5. Reg. Write

CS61C L20 Single Cycle Datapath, Control (4) Chae, Summer 2008 © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

CS61C L20 Single Cycle Datapath, Control (5) Chae, Summer 2008 © UCB Step 3: Assemble DataPath meeting requirements Register Transfer Requirements  Datapath Assembly Instruction Fetch Read Operands and Execute Operation

CS61C L20 Single Cycle Datapath, Control (6) Chae, Summer 2008 © UCB 3a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC  PC + 4 -Branch and Jump: PC  “something else” 32 Instruction Word Address Instruction Memory PC clk Next Address Logic

CS61C L20 Single Cycle Datapath, Control (7) Chae, Summer 2008 © UCB 3b: Add & Subtract R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU oprsrtrdshamtfunct bits 5 bits Already defined the register file & ALU

CS61C L20 Single Cycle Datapath, Control (8) Chae, Summer 2008 © UCB Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay “Critical path” (longest path through logic) determines length of clock period Clk

CS61C L20 Single Cycle Datapath, Control (9) Chae, Summer 2008 © UCB Register-Register Timing: One complete cycle Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

CS61C L20 Single Cycle Datapath, Control (10) Chae, Summer 2008 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate bits16 bits5 bits immediate bits ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd But we’re writing to Rt register??

CS61C L20 Single Cycle Datapath, Control (11) Chae, Summer 2008 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate bits16 bits5 bits immediate bits Already defined 32-bit MUX; Zero Ext? What about Rt register read?? 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc ALU 5 RegDst

CS61C L20 Single Cycle Datapath, Control (12) Chae, Summer 2008 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc ALU 5 RegDst

CS61C L20 Single Cycle Datapath, Control (13) Chae, Summer 2008 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5 ?

CS61C L20 Single Cycle Datapath, Control (14) Chae, Summer 2008 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5

CS61C L20 Single Cycle Datapath, Control (15) Chae, Summer 2008 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5

CS61C L20 Single Cycle Datapath, Control (16) Chae, Summer 2008 © UCB 3f: The Branch Instruction beq rs, rt, imm16 mem[PC] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction’s address -PC = PC ( SignExt(imm16) x 4 ) else -PC = PC + 4 oprsrtimmediate bits16 bits5 bits

CS61C L20 Single Cycle Datapath, Control (17) Chae, Summer 2008 © UCB Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate bits16 bits5 bits Already have mux, adder, need special sign extender for PC, need equal compare (sub?) imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 = Equal

CS61C L20 Single Cycle Datapath, Control (18) Chae, Summer 2008 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr Equal Instruction Imm16RdRtRs clk PC 00 4 nPC_sel PC Ext Adr Inst Memory Adder Mux = ALU 0 1 WrEnAdr Data Memory 5

CS61C L20 Single Cycle Datapath, Control (19) Chae, Summer 2008 © UCB Peer Instruction A. For the CPU designed so far, the Controller only needs to look at opcode/funct and Equal B. Adding jal would only require changing the Instruction Fetch block C. Making our single-cycle CPU multi-cycle will be easy ABC 0: FFF 1: FFT 2: FTF 3: FTT 4: TFF 5: TFT 6: TTF 7: TTT

CS61C L20 Single Cycle Datapath, Control (20) Chae, Summer 2008 © UCB Administrivia HW4 Due Friday 7/25 Cut out problem 8 HW5 out tonight, due next Tuesday 7/29 HW1,2 Grade Freeze Submit appeals by Friday 7/25

CS61C L20 Single Cycle Datapath, Control (21) Chae, Summer 2008 © UCB An Abstract View of the Implementation Data Out clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions clk ALU

CS61C L20 Single Cycle Datapath, Control (22) Chae, Summer 2008 © UCB An Abstract View of the Critical Path Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address clk ALU (Assumes a fast controller)

CS61C L20 Single Cycle Datapath, Control (23) Chae, Summer 2008 © UCB Halfway there: A Single Cycle Datapath 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel instr fetch unit clk We have everything except control signals

CS61C L20 Single Cycle Datapath, Control (24) Chae, Summer 2008 © UCB Meaning of the Control Signals nPC_sel: “+4” 0  PC <– PC + 4 “br” 1  PC <– PC {SignExt(Im16), 00 } Later in lecture: higher-level connection between mux and branch condition “n”=next imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 0 1

CS61C L20 Single Cycle Datapath, Control (25) Chae, Summer 2008 © UCB Meaning of the Control Signals ExtOp:“zero”, “sign” ALUsrc:0  regB; 1  immed ALUctr:“ ADD ”, “ SUB ”, “ OR ” °MemWr:1  write memory °MemtoReg: 0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5

CS61C L20 Single Cycle Datapath, Control (26) Chae, Summer 2008 © UCB RTL: The Add Instruction add rd, rs, rt MEM[PC]Fetch the instruction from memory R[rd] = R[rs] + R[rt]The actual operation PC = PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits

CS61C L20 Single Cycle Datapath, Control (27) Chae, Summer 2008 © UCB Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction = MEM[PC] same for all instructions imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address Inst Memory Instruction

CS61C L20 Single Cycle Datapath, Control (28) Chae, Summer 2008 © UCB The Single Cycle Datapath during Add R[rd] = R[rs] + R[rt] oprsrtrdshamtfunct ALUctr= ADD clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=1 Extender 3216 imm16 ALUSrc=0 ExtOp=x MemtoReg=0 clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (29) Chae, Summer 2008 © UCB Instruction Fetch Unit at the End of Add PC = PC + 4 This is the same for all instructions except: Branch and Jump imm16 clk PC 00 4 nPC_sel=+4 PC Ext Adder Mux Inst Address Inst Memory

CS61C L20 Single Cycle Datapath, Control (30) Chae, Summer 2008 © UCB Single Cycle Datapath during Or Immediate? oprsrtimmediate R[rt] = R[rs] OR ZeroExt[Imm16] 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (31) Chae, Summer 2008 © UCB R[rt] = R[rs] OR ZeroExt[Imm16] oprsrtimmediate Single Cycle Datapath during Or Immediate? 32 ALUctr= OR clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=0 Extender 3216 imm16 ALUSrc=1 ExtOp=zero MemtoReg=0 clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (32) Chae, Summer 2008 © UCB The Single Cycle Datapath during Load? R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (33) Chae, Summer 2008 © UCB The Single Cycle Datapath during Load R[rt] = Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate ALUctr= ADD clk busW RegWr=1 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=0 Extender 3216 imm16 ALUSrc=1 ExtOp=sign MemtoReg=1 clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (34) Chae, Summer 2008 © UCB The Single Cycle Datapath during Store? oprsrtimmediate Data Memory {R[rs] + SignExt[imm16]} = R[rt] 32 ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (35) Chae, Summer 2008 © UCB The Single Cycle Datapath during Store Data Memory {R[rs] + SignExt[imm16]} = R[rt] oprsrtimmediate ALUctr= ADD clk busW RegWr=0 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=x Extender 3216 imm16 ALUSrc=1 ExtOp=sign MemtoReg=x clk Data In 32 MemWr=1 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=+4 instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (36) Chae, Summer 2008 © UCB The Single Cycle Datapath during Branch? if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate ALUctr= clk busW RegWr= 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst= Extender 3216 imm16 ALUSrc= ExtOp= MemtoReg= clk Data In 32 MemWr= zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel= instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (37) Chae, Summer 2008 © UCB The Single Cycle Datapath during Branch if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0 oprsrtimmediate ALUctr= SUB clk busW RegWr=0 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst=x Extender 3216 imm16 ALUSrc=0 ExtOp=x MemtoReg=x clk Data In 32 MemWr=0 zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel=br instr fetch unit clk

CS61C L20 Single Cycle Datapath, Control (38) Chae, Summer 2008 © UCB Instruction Fetch Unit at the End of Branch if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate What is encoding of nPC_sel? Direct MUX select? Branch inst. / not branch Let’s pick 2nd option Adr Inst Memory nPC_sel Instruction Zero nPC_sel Q: What logic gate? imm16 clk PC 00 4 PC Ext Adder Mux 0 1 MUX ctrl

CS61C L20 Single Cycle Datapath, Control (39) Chae, Summer 2008 © UCB Step 4: Given Datapath: RTL  Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

CS61C L20 Single Cycle Datapath, Control (40) Chae, Summer 2008 © UCB A Summary of the Control Signals (1/2) inst Register Transfer add R[rd]  R[rs] + R[rt];PC  PC + 4 ALUsrc = RegB, ALUctr = “ ADD ”, RegDst = rd, RegWr, nPC_sel = “+4” sub R[rd]  R[rs] – R[rt];PC  PC + 4 ALUsrc = RegB, ALUctr = “ SUB ”, RegDst = rd, RegWr, nPC_sel = “+4” ori R[rt]  R[rs] + zero_ext(Imm16); PC  PC + 4 ALUsrc = Im, Extop = “Z”,ALUctr = “ OR ”, RegDst = rt,RegWr, nPC_sel =“+4” lw R[rt]  MEM[ R[rs] + sign_ext(Imm16)];PC  PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ ADD ”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” sw MEM[ R[rs] + sign_ext(Imm16)]  R[rs];PC  PC + 4 ALUsrc = Im, Extop = “sn”, ALUctr = “ ADD ”, MemWr, nPC_sel = “+4” beq if ( R[rs] == R[rt] ) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4 nPC_sel = “br”, ALUctr = “ SUB ”

CS61C L20 Single Cycle Datapath, Control (41) Chae, Summer 2008 © UCB A Summary of the Control Signals (2/2) addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr x Add x Subtract Or Add x 1 x x 0 x x Subtract x x x 0 0 ? 1 x x optarget address oprsrtrdshamtfunct oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op Appendix A See We Don’t Care :-)

CS61C L20 Single Cycle Datapath, Control (42) Chae, Summer 2008 © UCB Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR ) ALUctr[1] = or where, rtype = ~op 5  ~op 4  ~op 3  ~op 2  ~op 1  ~op 0, ori = ~op 5  ~op 4  op 3  op 2  ~op 1  op 0 lw = op 5  ~op 4  ~op 3  ~op 2  op 1  op 0 sw = op 5  ~op 4  op 3  ~op 2  op 1  op 0 beq = ~op 5  ~op 4  ~op 3  op 2  ~op 1  ~op 0 jump = ~op 5  ~op 4  ~op 3  ~op 2  op 1  ~op 0 add = rtype  func 5  ~func 4  ~func 3  ~func 2  ~func 1  ~func 0 sub = rtype  func 5  ~func 4  ~func 3  ~func 2  func 1  ~func 0 How do we implement this in gates?

CS61C L20 Single Cycle Datapath, Control (43) Chae, Summer 2008 © UCB Controller Implementation add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1] “AND” logic “OR” logic opcodefunc

CS61C L20 Single Cycle Datapath, Control (44) Chae, Summer 2008 © UCB Peer Instruction A. MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ? B. ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp? C. “Don’t Care” signals are useful because we can simplify our PLA personality matrix. F / T? ABC 0: SRF 1: SRT 2: SEF 3: SET 4: BRF 5: BRT 6: BEF 7: BET

CS61C L20 Single Cycle Datapath, Control (45) Chae, Summer 2008 © UCB °5 steps to design a processor 1. Analyze instruction set  datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic Equations Design Circuits Summary: Single-cycle Processor Control Datapath Memory Processor Input Output

CS61C L20 Single Cycle Datapath, Control (46) Chae, Summer 2008 © UCB Bonus slides These are extra slides that used to be included in lecture notes, but have been moved to this, the “bonus” area to serve as a supplement. The slides will appear in the order they would have in the normal presentation

CS61C L20 Single Cycle Datapath, Control (47) Chae, Summer 2008 © UCB 32 ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel= The Single Cycle Datapath during Jump optarget address J-typejump 25 Jump= TA26

CS61C L20 Single Cycle Datapath, Control (48) Chae, Summer 2008 © UCB The Single Cycle Datapath during Jump 32 ALUctr =x Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = x ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction RdRsRt New PC = { PC[31..28], target address, 00 } nPC_sel=? Jump=1 Imm16 TA26 optarget address J-typejump 25

CS61C L20 Single Cycle Datapath, Control (49) Chae, Summer 2008 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address J-typejump 25 How do we modify this to account for jumps? Jump

CS61C L20 Single Cycle Datapath, Control (50) Chae, Summer 2008 © UCB Instruction Fetch Unit at the End of Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel New PC = { PC[31..28], target address, 00 } optarget address J-typejump 25 Mux 1 0 Jump TA 4 (MSBs) 00 Query Can Zero still get asserted? Does nPC_sel need to be 0? If not, what? 26