HCAL FIT 2002 HCAL Data Concentrator Status Report Gueorgui Antchev, Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University

HCAL FIT Feb 2002CMS HCAL -- E. Hazen2 DCC Engineering Status Two prototype boards working Successful transfer of simulated HTR data to VME “spy” buffer at full PCI speeds Simple event builder working – FPGA coding for more advanced version underway

HCAL FIT Feb 2002CMS HCAL -- E. Hazen3 DCC Demonstrator Data Concentrator Logic PMC PCI 33/32 33/64 33/32 to CPU DCC FPGA Universe PCI-VME Bridge S-Link (64) LSC SDRAM TTCRx One 3-channel receiver On PMC Adapter PCI Interfaces Not working Due to layout Error… Working since Fall Used for Source Test Development Finished

HCAL FIT Feb 2002CMS HCAL -- E. Hazen4 DCC Demonstrator Spare PMC Site for Testing DCC Logic Board S-Link LSC (Transmitter) TTCRx LVDS Serial Link Receiver

HCAL FIT Feb 2002CMS HCAL -- E. Hazen5 DCC Prototype PC-MIP Mezzanine Cards 3 Channel Link Receivers Data from HTR Modules Data Concentrator Logic PMC PCI 33/32 33/64 33/32 to RUI DCC FPGA Universe PCI-VME Bridge S-Link (64) LSC SDRAM TTCRx Overflow Warning Fast Busy To TTS

HCAL FIT Feb 2002CMS HCAL -- E. Hazen6 DCC – Final Configuration Trigger S-LINK DAQ S-LINK FPGA DCC Logic Mezzanine Card Spare Standard PMC Site (33MHz 64 bit) 3x Link Receiver TTCRx FE Data from HTR Cards (LVDS Serial) VME 9Ux400 VME Motherboard (Design ~Frozen) Proposed Transition Module Fast Timing/ Control 235 pin 2mm Connector

HCAL FIT Feb 2002CMS HCAL -- E. Hazen7 DCC Logic Board

HCAL FIT Feb 2002CMS HCAL -- E. Hazen8 DCC Xilinx Chip Port1 Port1 FIFO 4KB 16bit/66MHz Port2 Port2 FIFO 4KB TTCrx Contr. TTCrx FIFO 4KB DAQ FIFO Write 4KB Trig FIFO 32KB SPY FIFO 8KB Trig S-LINK Port Port 3 EVENT BUILDER DDR SDRAM control Write PORT Read PORT 32bit/128M Hz Arbiter 32 DAQ FIFO Write Port 3 Write DAQ FIFO Read 4KB DAQ FIFO Write XILINX -XC2V1000 LVDS Fast Monitoring PCI1 ACEX 32bit/33MHz PCI2 ACEX 32bit/33MHz TTCrx board 36bit/128MH z TTCF out 32bit PCI3 ACEX 32bit/33MHz Trig S-LINK 32bit/128MHz Port 3 FIFO Read 16words Port 3 FIFO Write 16words 8MB DDR SDRAM DAQ FIFO Read Port 3 Read DAQ FIFO Read Port 3 Read Port 3 Write DAQ S-LINK Main S-LINK Port 64bit/128MHz 32bit/128MHz 32bit/66MHz 16bit/66MHz 32bit/33MHz Address/Con tr. 64bit/128MHz 32bit/128MH z 1Mx8 FLASH JTAG XILINX Config. Monitor FIFO 4KB Complete? Preliminary ? To be done

HCAL FIT Feb 2002CMS HCAL -- E. Hazen9 DCC Logic Status Complete data path working PCI 1/2 masters working Event builder: –Preliminary version which just glues together HTR data as-is to form events DDR SDRAM (1Gbyte/sec) interface –Dual-port logic for DAQ FIFO and VME Spy FIFO –Working; identical logic in use on D0 STT Simple VME interface for control/spy

HCAL FIT Feb 2002CMS HCAL -- E. Hazen10 DCC Prototype Plans Short-term goal: bandwidth test –Currently 9 clocks PCI overhead per event For 100 byte events (typical) we get 240 Mbytes/s –Further testing/optimization underway Finish event builder –Need to settle HTR  DCC and DCC  FED formats Implement monitoring –What do we need to monitor? Lots of FPGA gates available Implement trigger S-Link output Test TTCRx input Integrate with HTR Prototype Use for test beam

HCAL FIT Feb 2002CMS HCAL -- E. Hazen11 DCC Production Design One more logic board prototype: –Transition module for two S-Links –TTC Fanout input –Final “fast monitoring/status” outputs Overall Status: –Motherboard and Link Receiver design done Production purchase soon (this year!) ~ $50k each –Logic board design could in principle be done by this summer, but would like to delay production as long as possible (from an engineering standpoint) Production cost also ~ $50k –S-Link Transition module is NEW HARDWARE No formal cost estimate, but should easily be funded by cost savings in remainder of DCC

HCAL FIT Feb 2002CMS HCAL -- E. Hazen12 Lehman 2001 Schedule Are we in trouble? Maybe… = new estimate