Performed by: Yifat Kuttner & Noam Gluzer Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Subject: Data Characteristic Influence Over Lock Time Full Integrated Experiment סמסטר חורף 2004/2005 1

Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Advanced technology and significant raise in the volume of transmitted data caused an increased demand for faster communication systems. The work in high frequencies causes a new set of problems, and requires many adjustments. Several parameters affect the success of transmitting data in high frequencies, including the physical layer and the data characterization. An experiment was designed at the high speed digital systems lab, for demonstrating to the students the different problems. This project presents a new experiment that will be added to the existing system. The new experiment will demonstrate the influence of data characterization over the transmission success, as expressed in the lock mechanism. Secondary targets of the project are to be familiar with high-speed phenomenon, understand the existing working environment, integrate different entities and studying the lock mechanism

System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The system consists of two boards: –FPGA evaluation board, which generates and analyzes data traffic –High Speed Serial Data Channels board (HSDC), which routes this traffic through different physical links The boards are PC-controlled, using a dedicated programs Data is transmitted from the FPGA to the HSDC board Lock Time is measured from the start of data transmission, until the 4x4 switch's CDR indicates lock The time is measured by counting 100MHz clocks For Traces experiment The data is routed through different traces to demonstrate gradual degradation in the received data, until lock cannot be achieved

System Block Diagram Lock Time Experiment המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5

5 System Block Diagram ‘Traces’ Experiment המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5