CPU Design Project Synthesis Report ELEC Dr. Agrawal Lee W. Lerner April 24, 2007

Outline Synthesis Goals Synthesis Goals Synthesis Design Flow Synthesis Design Flow Mentor Graphics IC Flow Design ToolsMentor Graphics IC Flow Design Tools Various other software tools used for design debugging and verificationVarious other software tools used for design debugging and verification Synthesis Results Synthesis Results Area and Delay reportsArea and Delay reports Netlist verificationNetlist verification Conclusions Conclusions Suggestions for improvementSuggestions for improvement

Synthesis Goals Take a verified design modeled in hardware description language (VHDL in our design project) Take a verified design modeled in hardware description language (VHDL in our design project) Generate a gate- level netlist for the circuit that optimizes either: Generate a gate- level netlist for the circuit that optimizes either: 1. Area1. Area 2. Delay2. Delay 3. Both (to a lesser extent)3. Both (to a lesser extent) Verify functionality of netlists generated Verify functionality of netlists generated Decide on synthesized netlist to proceed with in project design flow Decide on synthesized netlist to proceed with in project design flow

Synthesis Design Flow Mentor Graphics IC Design Flow tools used: Mentor Graphics IC Design Flow tools used: Leonardo Spectrum 8Leonardo Spectrum 8 Synthesize gate-level netlists optimized for area and delay from provided VHDL CPU design Synthesize gate-level netlists optimized for area and delay from provided VHDL CPU design FlextestFlextest Verify that synthesized gate-level netlists compile Verify that synthesized gate-level netlists compile

Synthesis Design Flow Leonardo Spectrum 8 Leonardo Spectrum 8 V. P. Nelson, Tutorial Documents for Mentor Graphics Tools,

Synthesis Design Flow Netlists generated and corresponding reports: Netlists generated and corresponding reports: 1. Area Optimization (CPU_areaOpt.edf)1. Area Optimization (CPU_areaOpt.edf) Area report: areaOpt_areaReport Area report: areaOpt_areaReport Delay report: areaOpt_delayReport Delay report: areaOpt_delayReport 1. Delay Optimization (CPU_delayOpt.edf)1. Delay Optimization (CPU_delayOpt.edf) Area report: delayOpt_areaReport Area report: delayOpt_areaReport Delay report: delayOpt_delayReport Delay report: delayOpt_delayReport

Synthesis Results areaOpt_areaReport areaOpt_areaReport

Synthesis Results areaOpt_delayReport areaOpt_delayReport

Synthesis Results delayOpt_areaReport delayOpt_areaReport

Synthesis Results delayOpt_delayReport delayOpt_delayReport

Synthesis Results Netlist comparison Netlist comparison Area OptimizationNumber of ports111 Number of nets8249 Number of instances7601 Number of references to this view0 Number of gates16264 Number of accumulated instances7601 data arrival time18.06 ns Delay OptimizationNumber of ports111 Number of nets8343 Number of instances7696 Number of references to this view0 Number of gates16280 Number of accumulated instances7696 data arrival time18.22 ns

Synthesis Results Synthesis Verication: FlexTest Synthesis Verication: FlexTest Need for DFT (scan design) Need for DFT (scan design) Netlists compile correctly Netlists compile correctly

Conclusions Used Leonardo Spectrum 8 to generate gate-level netlists optimized for area and delay independently Used Leonardo Spectrum 8 to generate gate-level netlists optimized for area and delay independently Netlists compile correctly Netlists compile correctly Due to area and delay similarity between generated netlists it was decided that we could proceed with either netlist in the design project Due to area and delay similarity between generated netlists it was decided that we could proceed with either netlist in the design project

Conclusions Suggestions for improvement Suggestions for improvement Improved communication between team members (i.e. weekly status reports/presentations)Improved communication between team members (i.e. weekly status reports/presentations) Every team member has input at each stage in the design Every team member has input at each stage in the design Identify coding and design errors earlier Identify coding and design errors earlier Identify need for and implement DFT before synthesis Identify need for and implement DFT before synthesis Improved CPU design in a shorter time Improved CPU design in a shorter time