Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization Lei He, Andrew B. Kahng* #, Kingho Tam, Jinjun Xiong EE Department, University of California, Los Angeles *ECE and CSE Depts., University of California, San Diego # Blaze DFM, Inc., Sunnyvale SPIE-2005 Design-Process Integration March 3, 2004

Fill Pattern  Fill pattern inserted between “active” interconnects –Blue: active interconnect –Gray: dummy fill  Subset of potential fill patterns: –Rectangular shapes –Isothetic (aligned with axes)  Characterized by: –Number of rows (M=5) –Number of columns (N=3) –Series of widths (W) –Series of lengths (L) –Series of horizontal spacings (Sx) –Series of vertical spacings (Sy)

Performance-Driven Fill (DAC-2003)  Dummy fill increases capacitance, delay, crosstalk –  Insert fill where layout and timing can best tolerate it Full solution: Timing path driven, multi-layer aware This work addresses: How much can the fill pattern matter?

Driving Questions  How much does fill affect coupling and total capacitance?  How much do dishing and erosion affect interconnect performance?  What QOR loss is incurred by CMP-oblivious interconnect design?  Ultimately leading to: –CMP-aware fill pattern synthesis –CMP-aware fill and interconnect pattern synthesis –CMP-and fill-aware routing –CMP simulation drives performance analysis, layout signoff

Outline  Introduction and study goals  Impact of fill insertion and fill patterns  Impact of dishing/erosion on RC parasitics  Impact on interconnect design  Conclusions  Note: This talk = outline of methodology and analysis framework to drive full-chip place/route

Fill Pattern Concerns  How much can fill patterns affect interconnect cap?  What is the range of capacitance impact across “equivalent” fill patterns? –“Equivalence” is with respect to multi-layer CMP modeling, per-feature defocus budgeting, etc.

Distribution Characteristic Function  Given a total budget (e.g., width, length, spacing), distribute the budget to a given series (e.g., widths) via a Distribution Characteristic Function –Uniform –Linear increasing –Linear decreasing –Convex triangular

DCF for Fill Pattern Exploration  Different DCF combinations for width, length, and spacing series result in different fill patterns  Facilitates exploration of wide range of fill patterns –Enumeration is infeasible –Runtime and flexibility of capacitance extraction are another limit

Simulation Experiments: Setup  Interconnect models: Stripline (G-M-G)  Global interconnects at 65nm –Local metal density: 0.1~0.7 –Spacing (s) = (3-10) x minimum spacing (0.24um) –Width (w) = minimum width (0.24um) –Length (l) = 1000um –Metal thickness (0.50um) –ILD thickness (0.45um)  Three types of DCF for fill pattern exploration –Uniform –Linear increasing –Linear decreasing  All fills are floating  QuickCap used for capacitance extraction

Distribution of Coupling Capacitance  Local metal density = 0.3  Blue: nominal Cc without fill insertion  Red: Cc with different fill patterns (min – mean – max)

Distribution of Total Capacitance  Similar observations hold for Cs  Relative change of Cs is less dramatic than that of Cc  Still, more than 10% relative change compared to the nominal case

Coupling Cap vs. Total Cap  Fill always increases Cc/Cs –The gap (maximum – minimum) = potential variation due to fill insertion  Metal spacing increases  Cc/Cs also increases  Local metal density increases  Cc/Cs also increases  Note: Cc/Cs < 20% in our studies

Mini-Conclusion: Fill Insertion and Fill Pattern  Fill insertion can dramatically increase C c and C s over their respective nominal values –Cc 25%~300%, Cs ~10%  Cc and Cs varies significantly across different fill patterns –Relative change is more prominent for Cc than for Cs  Therefore, to obtain robust designs that will meet requirements (e.g., delay and parametric yield) after fill insertion, the variation (increase) of both Cc and Cs must be considered by the design flow.

Outline  Introduction and study goals  Impact of fill insertion and fill patterns  Impact of dishing/erosion on RC parasitics  Impact on interconnect design  Conclusions

Multi-step CMP Process Modeling and Simulation  Three step model of CMP process –Step 1 eliminates all local step heights, and irrelevant to the modeling of dishing and erosion. –Step 2 removes copper above trench, no dishing and erosion at the moment when pad reaches the barrier –Step 3: simultaneous oxide/copper polishing –Details: Gbondo-Tugbawa Ph.D. Thesis 2002

Impact on Global Interconnect Resistance  R f due to dishing/erosion is large: 28.7%~31.7% –Reduced cross-section  As width (w) grows, variation also increases  Spacing has little impact, as effective metal density is enforced Width w (μm) Spacing (μm) Nominal R o (kΩ) Real R f (kΩ) (+28.7%) (+30.6%) (+31.4%) (+28.8%) (+30.9%) (+31.7%)

Impact on Global Interconnect Capacitance  Three scenarios: –Interconnect with nominal value –Interconnect affected by dishing/erosion, WITHOUT fill insertion –Interconnect affected by dishing/erosion, WITH fill insertion  Dishing and erosion have comparatively smaller impact on capacitance  Fact of fill insertion has much larger impact on capacitance WS NOMINALDishing/ErosionFill+Dishing/Erosion CcCsCcCsCcCs (-2.63%) (-0.33%) 9.30 (33.06%) (-0.11%) (-3.78%) (-0.19%) 9.14 (26.33%) (-1.35%) (2.97%) (0.68%) 8.87 (26.51%) (-0.23%)

Mini-Conclusion on Dishing/Erosion Impact  Dishing and erosion impact on resistance: significant  Dishing and erosion impact on capacitance: ignorable –Assessment is design- and methodology- dependent  Fill insertion has much larger impact than dishing/erosion on capacitance

Outline  Introduction and study goals  Impact of fill insertion and fill patterns  Impact of dishing/erosion on RC parasitics  Impact on interconnect design  Conclusions

CMP-aware RC Methodology  Tabulate extracted capacitance –active interconnect width, spacing, local metal density  Capacitance table only saves the capacitance under the best (worst) fill pattern –Best = minimum Cc –Worst = maximum Cc  Resistance calculated from multi-step CMP model  CMP-aware RC Model –Fill insertion + Dishing & Erosion  CMP-oblivious RC Model –Nominal geometry only

Interconnect Design Concerns  How do CMP effects change conventional CMP-oblivious interconnect design ?  How do we take CMP effects into account for a better CMP- aware design flow?

Experiment Setup  Interconnect design for WIDE parallel bus –Four parallel, capacitively-coupled wires –Minimum # of elements, yet captures the “worst" case coupling effects  Goal: minimize “unit length delay” (D L ) –Vary buffer size (S) and interconnect length (L) between buffers

Experiment Results Under Best-Fill  CMP-oblivious design –Post “best-fill” insertion –Best “possible” practice for FAIR comparison  CMP-aware designs always result in smaller unit length delay –Relative improvement up to 3.3% –Improvement decreases as effective metal density increases Diminishing amount of erosion  Reduced resistance  Buffer area measured by S/L –CMP-aware design increases S/L by 14.8% Local Den. Eff. Den CMP-obliviousCMP-aware LSDLSS/L%DD%

Experiment Results Under Worst-Fill  Post worst-fill insertion: CMP-aware designs still result in smaller unit length delay –Relative improvement up to 3.5%  Post best-fill insertion: CMP-aware design not necessary better  Therefore, no single design that is CMP-variation optimal –Design for specific fill pattern in order to attain optimality Local Den. Eff. Den CMP-obliviousCMP-aware LSDLSS/L%DD% Verified under post worst-fill insertion Verified under post best-fill insertion

Outline  Introduction and study goals  Impact of fill insertion and fill patterns  Impact of dishing/erosion on RC parasitics  Impact on interconnect design  Conclusions

Conclusions  Dummy fill can cause substantial coupling capacitance variation with respect to nominal –Grounded track fill  even more impact  Dishing and erosion cause substantial resistance increase, but have limited impact on coupling  CMP-aware design can improve design quality –Improve unit length delay by 3.3% under best-fill  Ongoing directions –Integration of multi-layer CMP modeling into flow –CMP-aware fill pattern synthesis, then single- interconnect wire and buffer sizing, then full routing –Study the impact from more sources of variations on interconnect performance and design