1 Area Fill Generation With Inherent Data Volume Reduction Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky and Yuhong Zheng (UCLA, UCSD,

Slides:



Advertisements
Similar presentations
Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. NSF, and the Packard Foundation Y. Chen, A. B. Kahng, G. Robins,
Advertisements

New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout Andrew B. Kahng (UCSD) Shailesh Vaya (UCLA) Alex Zelikovsky.
Quality Aware Privacy Protection for Location-based Services Zhen Xiao, Xiaofeng Meng Renmin University of China Jianliang Xu Hong Kong Baptist University.
DPIMM-II 2003 UCSD VLSI CAD LAB Compression Schemes for "Dummy Fill" VLSI Layout Data Robert Ellis, Andrew B. Kahng and Yuhong Zheng ( Texas A&M University.
Coverage by Directional Sensors Jing Ai and Alhussein A. Abouzeid Dept. of Electrical, Computer and Systems Engineering Rensselaer Polytechnic Institute.
1 EE5900 Advanced Embedded System For Smart Infrastructure Static Scheduling.
Optimization of Linear Placements for Wirelength Minimization with Free Sites A. B. Kahng, P. Tucker, A. Zelikovsky (UCLA & UCSD) Supported by grants from.
S. J. Shyu Chap. 1 Introduction 1 The Design and Analysis of Algorithms Chapter 1 Introduction S. J. Shyu.
Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University.
© Yamacraw, 2001 Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability A. Zelikovsky GSU Joint work with C. Alpert.
Greedy vs Dynamic Programming Approach
Approximating Sensor Network Queries Using In-Network Summaries Alexandra Meliou Carlos Guestrin Joseph Hellerstein.
Minimum-Buffered Routing of Non- Critical Nets for Slew Rate and Reliability Control Supported by Cadence Design Systems, Inc. and the MARCO Gigascale.
Border Length Minimization in DNA Array Design A.B. Kahng, I.I. Mandoiu, P. Pevzner, S. Reda (all UCSD), A. Zelikovsky (GSU)
Background: Scan-Based Delay Fault Testing Sequentially apply initialization, launch test vector pairs that differ by 1-bit shift A vector pair induces.
Recent Development on Elimination Ordering Group 1.
1 Optimization problems such as MAXSAT, MIN NODE COVER, MAX INDEPENDENT SET, MAX CLIQUE, MIN SET COVER, TSP, KNAPSACK, BINPACKING do not have a polynomial.
Monte-Carlo Methods for Chemical-Mechanical Planarization on Multiple-Layer and Dual-Material Models Supported by Cadence Design Systems, Inc., NSF, the.
: Grid graph :Draw two rays from each concave point Rays are divided into non-intersected ray-segments Conflict pair: two ray segments from the same point.
Performance-Impact Limited Area Fill Synthesis
Fill for Shallow Trench Isolation CMP
Zoë Abrams, Ashish Goel, Serge Plotkin Stanford University Set K-Cover Algorithms for Energy Efficient Monitoring in Wireless Sensor Networks.
Yield- and Cost-Driven Fracturing for Variable Shaped-Beam Mask Writing Andrew B. Kahng CSE and ECE Departments, UCSD Xu Xu CSE Department, UCSD Alex Zelikovsky.
Practical Iterated Fill Synthesis for CMP Uniformity Supported by Cadence Design Systems, Inc. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UVA.
Measurement of Inherent Noise in EDA Tools Andrew B. Kahng* and Stefanus Mantik * UCSD CSE and ECE Departments, La Jolla, CA UCLA CS Department, Los Angeles,
DPIMM-03 1 Performance-Impact Limited Area Fill Synthesis Yu Chen, Puneet Gupta, Andrew B. Kahng (UCLA, UCSD) Supported by Cadence.
Jan 6-10th, 2007VLSI Design A Reduced Complexity Algorithm for Minimizing N-Detect Tests Kalyana R. Kantipudi Vishwani D. Agrawal Department of Electrical.
Fill for Shallow Trench Isolation CMP Andrew B. Kahng 1,2 Puneet Sharma 1 Alexander Zelikovsky 3 1 ECE Department, University of California – San Diego.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 5: February 2, 2009 Architecture Synthesis (Provisioning, Allocation)
Design Bright-Field AAPSM Conflict Detection and Correction C. Chiang, Synopsys A. Kahng, UC San Diego S. Sinha, Synopsys X. Xu, UC San Diego A. Zelikovsky,
Achieving Minimum Coverage Breach under Bandwidth Constraints in Wireless Sensor Networks Maggie X. Cheng, Lu Ruan and Weili Wu Dept. of Comput. Sci, Missouri.
UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.
Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization Lei He, Andrew B. Kahng*, Kingho Tam, Jinjun Xiong.
Border Length Minimization in DNA Array Design A.B. Kahng, I.I. Mandoiu, P.A. Pevzner, S. Reda (all UCSD), A. Zelikovsky (GSU)
UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD.
Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky (UCLA, UCSD, UVA.
7/14/ Design for Manufacturability Prof. Shiyan Hu Office: EERC 731.
Abstract A new Open Artwork System Interchange Standard (OASIS) has been recently proposed for replacing the GDSII format. A primary objective of the new.
1 Combinatorial Problems in Cooperative Control: Complexity and Scalability Carla Gomes and Bart Selman Cornell University Muri Meeting March 2002.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 5: February 2, 2009 Architecture Synthesis (Provisioning, Allocation)
Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. NSF, and the Packard Foundation Y. Chen, A. B. Kahng, G. Robins,
07/21/2005 Senmetrics1 Xin Liu Computer Science Department University of California, Davis Joint work with P. Mohapatra On the Deployment of Wireless Sensor.
Planning Production of a Set of Semiconductor Components with Uncertain Wafer and Component Yield Frank W. Ciarallo Assistant Professor Biomedical, Industrial.
1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese.
1 Introduction to Approximation Algorithms. 2 NP-completeness Do your best then.
UC San Diego / VLSI CAD Laboratory Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion Andrew B. Kahng, Ilgweon Kang and Siddhartha Nath.
NTUEE 1 Coupling-Constrained Dummy Fill for Density Gradient Minimization Huang-Yu Chen 1, Szu-Jui Chou 2, and Yao-Wen Chang 1 1 National Taiwan University,
Maximum Network Lifetime in Wireless Sensor Networks with Adjustable Sensing Ranges Cardei, M.; Jie Wu; Mingming Lu; Pervaiz, M.O.; Wireless And Mobile.
ICPP 2012 Indexing and Parallel Query Processing Support for Visualizing Climate Datasets Yu Su*, Gagan Agrawal*, Jonathan Woodring † *The Ohio State University.
Kwangsoo Han, Andrew B. Kahng, Hyein Lee and Lutong Wang
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis Supported by Cadence Design Systems, Inc., NSF, the Packard Foundation, and State of Georgia’s.
Scalable Symbolic Model Order Reduction Yiyu Shi*, Lei He* and C. J. Richard Shi + *Electrical Engineering Department, UCLA + Electrical Engineering Department,
 Chemical-Mechanical Polishing (CMP)  Rotating pad polishes each layer on wafers to achieve planarized surfaces  Uneven features cause polishing pad.
Competitive Queue Policies for Differentiated Services Seminar in Packet Networks1 Competitive Queue Policies for Differentiated Services William.
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis Supported by Cadence Design Systems, Inc., NSF, the Packard Foundation, and State of Georgia’s.
1 Approximation algorithms Algorithms and Networks 2015/2016 Hans L. Bodlaender Johan M. M. van Rooij TexPoint fonts used in EMF. Read the TexPoint manual.
© The McGraw-Hill Companies, Inc., Chapter 1 Introduction.
A Fully Polynomial Time Approximation Scheme for Timing Driven Minimum Cost Buffer Insertion Shiyan Hu*, Zhuo Li**, Charles Alpert** *Dept of Electrical.
Hypergraph Partitioning With Fixed Vertices Andrew E. Caldwell, Andrew B. Kahng and Igor L. Markov UCLA Computer Science Department
TU/e Algorithms (2IL15) – Lecture 12 1 Linear Programming.
Efficient Point Coverage in Wireless Sensor Networks Jie Wang and Ning Zhong Department of Computer Science University of Massachusetts Journal of Combinatorial.
CS 721 Project Implementation of Hypergraph Edge Covering Algorithms By David Leung ( )
1 Chapter 5 Branch-and-bound Framework and Its Applications.
TU/e Algorithms (2IL15) – Lecture 12 1 Linear Programming.
11 Yibo Lin 1, Xiaoqing Xu 1, Bei Yu 2, Ross Baldick 1, David Z. Pan 1 1 ECE Department, University of Texas at Austin 2 CSE Department, Chinese University.
Approximation algorithms
Approximation algorithms
Closing the Smoothness and Uniformity Gap in Area Fill Synthesis
Maximum Lifetime of Sensor Networks with Adjustable Sensing Range
CUBE MATERIALIZATION E0 261 Jayant Haritsa
Presentation transcript:

1 Area Fill Generation With Inherent Data Volume Reduction Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky and Yuhong Zheng (UCLA, UCSD, UVA, GSU) Supported by Cadence Design Systems, Inc., NSF, the Packard Foundation, and State of Georgia’s Yamacraw Initiative

2 CMP and Interlevel Dielectric Thickness  Chemical-Mechanical Planarization (CMP) = wafer surface planarization  Uneven features cause polishing pad to deform  Interlevel-dielectric (ILD) thickness  feature density  Insert dummy features to decrease variation Post-CMP ILD thickness Features Area fill features Post-CMP ILD thickness

3 Fill Compression Problem  Compressible Fill Generation Problem (CFGP) Given a design rule-correct layout, create the minimum number of GDSII AREFs to represent area fill features such that the window density variation is within the given bounds (L,U) Original layout Filled layout with 82 area features Filled layout with area features in 9 AREFs

4 Fill Compression in Fixed-Dissection Regime Original layout in fixed-dissection regime windows tile Tile with original features Grid the tile with feature size Satisfy fixed fill requirement (e.g., 56 fill features) with minimum number of AREFs (e.g., 4 AREFs)  Fixed CFGP in Fixed-Dissection Regime l Given a design rule-correct layout consisting of tiles, the site arrays for each tile, and fill requirement for each tile, create the minimum number of AREFs to represent area fill features such that each tile contains exactly area fill features Tile with original features Grid the tile with feature size Satisfy ranged fill requirement (e.g., 50 ~ 60 fill features) with minimum number of AREFs (e.g., 3 AREFs)  Ranged CFGP in Fixed-Dissection Regime l Given a design rule-correct layout consisting of tiles, the site arrays for each tile, and fill requirement range for each tile, create the minimum number of AREFs to represent area fill features such that each tile contains a number of area fill features in the range

5 Linear Programming Based Methods  Main idea: l Find minimum #AREFs in free sites for given fill requirements  Single-Tile Integer LP Formulations site in position (p,q) in tile (i,j)feasible AREF in layout is covered by AREF otherwise AREF is chosen if is occupied by original features Minimize: # covered slack sites = given # fill features all sites covered by AREF are filled only the sites covered by AREF can be filled

6 Compressible Fill Generation with AREF  Multiple-Tile Integer LP Formulations l Ideally consider fill compression on entire layout at one time l Multiple-tile compression as a tradeoff for tiles  Ranged Fill Compression l Exploit allowed range of fill features for each tile l Single-Tile l Multiple-Tile for tiles

7 Greedy Speedup Approaches  Greedy Speedup Approach 1 (GS-1) l Find the largest AREFs originating from each free site l Pick the AREF that fills the maximum number of free sites but does not overfill the tiles if such an AREF exists l Otherwise, select the maximum AREF from the largest AREFs, and take one of its sub-AREFs which do not overfill the tiles  Time complexity of the algorithm is reduced to O(n 3 )  Motivation of Speedup l Strict greedy heuristic -O(n4) time complexity -Provide good solutions but is impractical l Greedy speedup schemes -Trade-off between time complexity and compression performance -Pick acceptable AREFs instead of maximal AREFs

8 Greedy Speedup Approaches (cont’d)  Greedy Speedup Approach 2 (GS-2) l Pick the acceptable AREFs originating from each free site l Criteria of an acceptable AREF: -Size is smaller than K  L -Fill maximum free sites but does not overfill the tiles l Time complexity of the algorithm is reduced to O(KLn2)  GS-1 vs. GS-2 l Compared to GS-1, GS-2 achieves better tradeoff between compression results and time complexity. While K·L << n, GS-2 results are just ~4% worse but ~39× faster than GS-1 based on our experiments. l GS-1 cannot guarantee better behavior with multiple-tile option than with single-tile option because the sets of the largest AREFs are different for the single-tile option and the multiple-tile option l GS-2 does guarantee better behavior with multiple-tile option

9 Experiments: Greedy Speedup Approaches  Greedy approach can achieves very large compression ratios, especially when the fill features are small  GS-1 gets better results for single-tile than for multiple-tile  GS-2 results are always better for multiple-tile than for single-tile

10 Experiments: Greedy Speedup Approaches  GS-2 achieves better tradeoff between performance and runtime  GS-2 is much faster than GS-1, with only small quality degradation

11 Comparison of fill compression methods  Performance of GS-1 is very close to optimal ILP method  GS-1 is more efficient in run time than ILP method

12 Conclusions & Future Works  Contributions: l New compressed fill strategies with AREF to reduce data volume l Linear programming based methods l Greedy based optimization methods  Future Works l Improve compression ratios and scalability l Exploit new standard layout format -Open Artwork System Interchange Standard (OASIS) l Compressible fill generation problem with underlying layout hierarchy

13 Thank You!