Balancing Interconnect and Computation in a Reconfigurable Array Dr. André DeHon BRASS Project University of California at Berkeley Why you don’t really want 100% LUT utilization

Question How much interconnect do I need for my computing/programmable array? Problem(?): too little interconnect  won’t be able to use all the gates/LUTs Typical subgoal: how much interconnect to use (almost) all LUTs?

Wrong Subgoal Observation: –interconnect is dominant area on FPGAs –more important to use interconnect efficiently than to use LUTs efficiently Different question/subgoal: –What level of interconnect gives the least implementation area for applications?

LUT Utilization predict Area?

Outline Question: how much interconnect? Teaser: less than 100% LUT utilization Model Application characteristics Compose Conclusions

Model Interconnect Requirements and Richness Recursively partition (bisect) design –Look at I/O from each partition (subtree) N/2 cutsize

Regularizing Growth How do bisection bandwidths shrink (grow) at different levels of bisection hierarchy? Basic assumption: Geometric –1 –1/  –1/  2

Rent’s Rule Long standing empirical relationship –IO = C  N P –0  P  1.0 Embodies geometric assumption (C,P) –Two parameters C base of growth P capture growth (  = 2 P ) Captures notion of locality

Define Network with Parameters (2 1)* =>  =  2 (2 2 1)* =>  =(2*2) (1/3) =2 (2/3) ( )* =>  =2 (3/4)

“Cartoon” VLSI Area Model (Example artificially small for clarity)

Effects of P on Area 0.25 P= P= P= LUT Area Comparison

Application Requirements: Benchmark Wide (MCNC)

Benchmark Parameters Interconnect requirements vary across applications.

Network Fixed Schedule Network will have a fixed wiring schedule Applications have varying requirements To assess impact of mismatch –map to network schedules –look at area required

Mapping Problem When design interconnect exceeds network –have to repartition to meet fixed wire schedules of target network –depopulating LUTs as necessary See paper/poster for one approach

Resources  Area Model => Area

Picking Network Design Point (8 wire pitch; switchpoints; linear population)

Summary Interconnect area dominates logic block area Interconnect requirements vary –among designs –within a single design To minimize area –focus on using dominant resource (interconnect) –may underuse non-dominant resources (LUTs)