RAVEN: Automatic Generation of Analog Behavioral Models Chandramouli Kashyap Chirayu Amin Reshma Kamat Design Technology Solutions, Intel Corp.

Why is this an important problem IO bandwidth increasing + tighter specs => increased analog complexity More variety of analog circuits: IO, sensor, fuse, PLLs Analog circuits adaptively controlled by digital analog digital Ensure correct digital/analog interactions

Problem with analog abstraction digital Mixed-signal simulator analog Verilog- AMS FEV accurate but slow need access to process models Verilog- reals Manual; quality varies greatly Fast but less accurate

What is Raven Spec/Config files RAVEN analog schematic Verilog-AMS SV with Reals

How Raven works Generate Spice runs Based on user spec Analyze waveforms Extract parameters Build look-up table Encode in Verilog

Input specs Type of input Type of excitation Range of inputs Digital vs analog, voltage vs current Type of excitation Periodic, step, ramp Range of inputs Min:step:max Range could be different for different modes

Types of output handled Periodic Extract period, pw, amplitude, phase offset wrt ref Transition Extract delay, final value Average Extract average over an interval T

Circuits successfully modeled Output type sigma-delta ADC average phase interpolator periodic VCO current DAC single transition TX with Pre-emphasis

What is Raven not good at Complex history dependent effects Any state nodes in the circuit need to be marked by user with their ranges

Summary and future work Raven can generate RTL abstractions of analog circuits Allows designer to focus on design and specs Can track netlist ECOs Raven models can be made PVT aware easily Can these models be used for FV using hybrid system techniques?