Computer ArchitectureFall 2007 © Sep 10 th, 2007 Majd F. Sakr CS-447– Computer Architecture M,W 10-11:20am Lecture 4 Instruction Set Architecture

Computer ArchitectureFall 2007 © Done by now °Read the first 3 chapters of the book °Review the slides °Come see us during office hours °Working on the project

Computer ArchitectureFall 2007 © Program Concept °Hardwired systems are inflexible °General purpose hardware can do different tasks, given correct control signals °Instead of re-wiring, supply a new set of control signals

Computer ArchitectureFall 2007 © What is a program? °A sequence of steps °For each step, an arithmetic or logical operation is done °For each operation, a different set of control signals are needed

Computer ArchitectureFall 2007 © Execution of a Program

Computer ArchitectureFall 2007 © Program -> Sequence of Instructions

Computer ArchitectureFall 2007 © Function of Control Unit °For each operation a unique code is provided e.g. ADD, MOVE °A hardware segment accepts the code and issues the control signals °We have a computer!

Computer ArchitectureFall 2007 © Computer Components: Top Level View

Computer ArchitectureFall 2007 © Instruction Cycle °Two steps: Fetch Execute

Computer ArchitectureFall 2007 © Fetch Cycle °Program Counter (PC) holds address of next instruction to fetch °Processor fetches instruction from memory location pointed to by PC °Increment PC (PC = PC + 1) Unless told otherwise °Instruction loaded into Instruction Register (IR) °Processor interprets instruction

Computer ArchitectureFall 2007 © Execute Cycle °Processor-memory data transfer between CPU and main memory °Processor I/O Data transfer between CPU and I/O module °Data processing Some arithmetic or logical operation on data °Control Alteration of sequence of operations e.g. jump °Combination of above

Computer ArchitectureFall 2007 © Instruction Set Architecture I/O systemProcessor Compiler Operating System (Windows XP) Application (MediaPlayer) Digital Design Circuit Design Instruction Set Architecture Datapath & Control Transistors Memory Hardware Software Assembler Layout & Technology The Language of the Computer

Computer ArchitectureFall 2007 © Chapter objectives °The goal of this lecture is to discuss an instruction set (a simple one), showing both how instructions are represented in hardware & the relationship between high-level programming languages (for example C- language which you know) and this more primitive one. °Next time: the different addressing modes.

Computer ArchitectureFall 2007 © °By learning how to represent instructions, you will also discover the secret of computing: the stored-program concept. Chapter objectives (2)

Computer ArchitectureFall 2007 © Translating & Starting a Program C Program Compiler Assembly Language Program Assembler Object: Machine language module Linker Executable: Machine language program

Computer ArchitectureFall 2007 © Translating & Optimizing a Program: The Compiler The Compiler transforms the C program into an assembly language program, a symbolic form of what the machine understands.

Computer ArchitectureFall 2007 © Translating a Program: The Assembler The Assembler transforms the Assembly program into a machine language module.

Computer ArchitectureFall 2007 © Stitching a Program: The Linker The linker or link editor takes all the independently assembled machine language programs and “stitches” them together. There are three steps for the linker: 1) Place code and data modules symbolically in memory 2) Determine the addresses of data and instruction labels 3) Patch both the internal and external references

Computer ArchitectureFall 2007 © What Happens in Hardware? CPUMemory Instructions Data

Computer ArchitectureFall 2007 © Address Bus & Data Bus Data Bus Address Bus CPUMemory

Computer ArchitectureFall 2007 © Address Bus & Data Bus Data Bus Address Bus CPUMemory °Address Bus: Names Locations Where to go °Data Bus: Content Values Variables

Computer ArchitectureFall 2007 © Memory Addressing

Computer ArchitectureFall 2007 © Example of Memory with AddrBus = 1 Decoder 1 to 2 Memory 0 1 DataBus = 1 Decoder 1 to 2 Memory 0 1 DataBus = 2 Address Bus = 1

Computer ArchitectureFall 2007 © Example of Memory with AddrBus = 1 Decoder 1 to 2 Memory 0 1 Address Bus = 1 Data Bus = 8

Computer ArchitectureFall 2007 © Example of Memory with AddrBus = 2 Decoder 2 to 4 Memory 0 1 DataBus = Address Bus = 2

Computer ArchitectureFall 2007 © Decoder 2 to 4 Memory 0 1 DataBus = Example of Memory with AddrBus = 2 Address Bus = 2

Computer ArchitectureFall 2007 © Decoder 2 to 4 Memory 0 1 DataBus = Example of Memory with AddrBus = 2 Address Bus = 2

Computer ArchitectureFall 2007 © How does the Memory look like? Location/AddressContent English Decimal Binary DecimalBinary ML ML ML ….….….…… ML ML ML

Computer ArchitectureFall 2007 © Memory Addresses Vs Memory Content As shown in the memory table: # locations = 64 (ML0 to ML63) => memory require 6-bits to address if the memory word-size = 11-bits => largest content in memory is 2048

Computer ArchitectureFall 2007 © In General we Need 2 #bits = # Memory Locations If we wish to have 120 locations (120 names), then 7-bits should be dedicated to address them (2 7 = 128) If we first decide to dedicate 6-bits to address the memory locations, then we will be limited to 64 in their number (2 6 = 64)

Computer ArchitectureFall 2007 © Instruction Set Design Data Bus Address Bus CPUMemory Control Register File Functional Units IR PC Instructions Data

Computer ArchitectureFall 2007 © What is an instruction set? °The complete collection of instructions that are understood by a CPU °Machine Code °Binary °Usually represented by assembly codes

Computer ArchitectureFall 2007 © Elements of an Instruction °Operation code (Op code) Do this operation °Source Operand reference To this to this value °Result Operand reference Put the answer here

Computer ArchitectureFall 2007 © Operation Code (page 342) °Operation code (Opcode) Do this operation NameMnemonic AdditionADD SubtractionSUB …… MultiplyMULT

Computer ArchitectureFall 2007 © Processor Operations: Data processing Data storage Data movement Program flow control °Add °Sub °Load °Store °Read °Write °GoTo °Branch I f In total, the # of instructions desired is 8, and these require 3-bits for controlling.

Computer ArchitectureFall 2007 © Registers & How Big? °CPU must have some working space (temporary storage) °Number of Registers varies between processor designs °Large enough to hold full address °Large enough to hold full data word

Computer ArchitectureFall 2007 © How does the Registers File look like? Name/AddressContent English Decimal Binary DecimalBinary R R R R R R R R

Computer ArchitectureFall 2007 © Register Address Vs Register Content As shown in the register file: # registers = 8 (R0 to R7) => registers require 3-bits to address if the register size = 11-bits => largest content in registers is 2047

Computer ArchitectureFall 2007 © In General we Need 2 #bits = # Registers If we wish to have 30 registers, then 5-bits should be dedicated to address them (2 5 = 32) If we first decide to dedicate 4-bits to address the registers, then we will be limited to 16 in their number (2 4 = 16)

Computer ArchitectureFall 2007 © Instruction Design Data processing Data storage Data movement Program flow control Sub000Load010Read100GoTo110 Add001Store011Write101Branch I f111 I want this operation to make the addition of two registers & place the result in a third one Example: Add R1, R2, R3 ; R1 = R2 + R3

Computer ArchitectureFall 2007 © Instruction Design If in our register file we had 4 registers, requiring 2-bits for addressing each; thus the 3 operands desired (R1, R2, R3) in the Add operation require (2x3 =) 6-bits to be addressed.

Computer ArchitectureFall 2007 © Instruction Design: Add R0, R4, R11 AddR1,R2,R OpCode Destination Register Source Register 3-bits2-bits 9-bits Instruction

Computer ArchitectureFall 2007 © Add R1, R2, R3 ;(= ) Register File Functional Units I.R. P.C CPU Memory What happens inside the CPU?

Computer ArchitectureFall 2007 © I.R. P.C Add R1, R2, R3 ;(= ) R1 R2 R Next Instruction 4 CPU

Computer ArchitectureFall 2007 © Hypothetical Machine Consider the following hypothetical machine: # registers = 16 {R0 to R15}  require 4-bits to address them (24 = 16) # memory locations = 256 {M0 to M255}  require 8-bits to address them (28 = 256)

Computer ArchitectureFall 2007 © Hypothetical Machine (cont’d) # instructions = 32{Inst0 to Inst31}  require 5-bits to be controlled (2 5 = 32) where Inst15 = Add (instruction # 15) & Inst9 = Load (instruction # 9)

Computer ArchitectureFall 2007 © Example 1: Add R0, R4, R11 AddR0,R4,R11 ; R0 = R4 + R And to make it simpler to read and use we will use the Hex notation F04B And the output of the assembler would simply be the following machine code: F04B

Computer ArchitectureFall 2007 © The instruction In fact, each piece of an instruction can be considered as an individual number, & placing these numbers side by side forms the instruction. OpCode Destination Register 1 Source Register 1 Source Register 2 5 bits4 bits 17-bit Instruction

Computer ArchitectureFall 2007 © Example 2: Load R13, 127 LoadR13,127 ; R13 = (127) And in the Hex notation 9D7 F And the output of the assembler would simply be the following machine code: 9D7F

Computer ArchitectureFall 2007 © The instruction In fact, the instruction format Example: OpCode, Operand, Operand, Operand is fixed only for a specific operation OpCodeRegisterMemory Address 5 bits4 bits8 bits 17-bit Instruction

Computer ArchitectureFall 2007 © Note °When the OpCode consist of a memory R/W, the operand, Source Register 1 & 2 are combined to form the address field of the instruction. °When the OpCode consist of an immediate instruction, the operand, Source Register 1 & 2 are combined to form the constant whenever that is required.

Computer ArchitectureFall 2007 © The Instruction °OpCode: basic operation of the instruction °Destination Register: register where the result of the operations will be loaded °Source Register 1 & 2: registers where the data will be operated on

Computer ArchitectureFall 2007 © Instruction size = data word size As you can see from counting the number of bits, this hypothetical machine instruction takes exactly 17-bits which should be the same size as a data word.

Computer ArchitectureFall 2007 © Design by Starting with the Instruction Size We would like to design a machine with: Instruction size = 8 bits Instruction number = 8 1.No Operation 2. Add 3. Sub 4. Branch 5. Load 6. Store 7. Increment 8. Decrement 3-bits of the instruction word will be reserved to control the 8 desired instructions xxx

Computer ArchitectureFall 2007 © So we are left with 5-bits for the operands, With which we can address at most: 32 (= 2 5 ) memory locations 32 (= 2 5 ) registers But if we chose to do so, we will be restricted in the number of operands in the instructions to one Design by Starting with the Instruction Size

Computer ArchitectureFall 2007 © On the other hand if we wish to have instructions with 2 explicit operands; that is still possible with the 5-bits left. Design by Starting with the Instruction Size xxx How ? ! ?

Computer ArchitectureFall 2007 © How ? ! ? Using bits 3 with 4 and bits 5 with 6 to address 4 registers. xxx BitsRegisters addressed# of Registers 3 with 4 R1, R2, R3, R44 5 with 6

Computer ArchitectureFall 2007 © Results °8 Instructions °2 operands addressing 4 registers with 2- bits each °1 operand of 5-bits addressing 32 memory locations Note: # operands increases # registers decreases

Computer ArchitectureFall 2007 © Consider this Instruction Set Data processing Data storage Data movement Program flow control Sub000Load010Read100GoTo110 Add001Store011Write101Branch I f111

Computer ArchitectureFall 2007 © Execution of a simple program The following program was loaded in memory starting from memory location Load R2, ML4 ; R2 = (ML4) = 5 = Read R3, Input14 ; R3 = input device 14 = Sub R1, R3, R2 ; R1 = R3 – R2 = 7 – 5 = Store R1, ML5 ; store (R1) = 2 in ML5

Computer ArchitectureFall 2007 © The Program in Memory LoadR2,ML ReadR3,Input SubR1,R3,R StoreR1,ML …… Don’t care Input Port Output Port Address Content

Computer ArchitectureFall 2007 © I.R. P.C LoadR2, ML4 ; Load... R1 R2 R CPU 1

Computer ArchitectureFall 2007 © ReadR3, Input14; Read... R1 R2 R CPU

Computer ArchitectureFall 2007 © SubR1, R3, R2; Sub... R1 R2 R CPU

Computer ArchitectureFall 2007 © Store R1, ML5; Don’t Care... R1 R2 R CPU Next Instruction Store

Computer ArchitectureFall 2007 © Before Program Execution In the Memory Don’t care …… Input Port Output Port Address Content After Program Execution