EE365 Adv. Digital Circuit Design Clarkson University Lecture #10 Latches, Flip Flops & Sequential PALS

Topics Basic Definitions Latches Edge-Triggered Flip-Flops Timing Requirements Rissacher EE365Lect #10

Sequential Circuits Output depends on current input and past history of inputs. “State” embodies all the information about the past needed to predict current output based on current input. –State variables, one or more bits of information. Rissacher EE365Lect #10

Describing Sequential Circuits State table –For each current-state, specify next-states as function of inputs –For each current-state, specify outputs as function of inputs Rissacher EE365Lect #10

Describing Sequential Circuits State diagram –Graphical version of state table Rissacher EE365Lect #10

Clock signals Very important with most sequential circuits –State variables change state at clock edge. Rissacher EE365Lect #10

Bistable element The simplest sequential circuit Two states –One state variable, say, Q HIGHLOW HIGH Rissacher EE365Lect #10

Bistable element The simplest sequential circuit Two states –One state variable, say, Q LOWHIGH LOW Rissacher EE365Lect #10

Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V Rissacher EE365Lect #10

Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 2.5 V Rissacher EE365Lect #10

Analog analysis Assume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 V 2.5 V 2.0 V 4.8 V 2.5 V2.51 V4.8 V0.0 V 5.0 V Rissacher EE365Lect #10

Metastability Metastability is inherent in any bistable circuit Two stable points, one metastable point Rissacher EE365Lect #10

Another look at metastability Rissacher EE365Lect #10

“sube y baja” behavior Rissacher EE365Lect #10

Why all the harping on metastability? All real systems are subject to it –Problems are caused by “asynchronous inputs” that do not meet flip-flop setup and hold times. –Details in Chapter-7 flip-flop descriptions and in Section 8.9 –Especially severe in high-speed systems – since clock periods are so short, “metastability resolution time” can be longer than one clock period. Many digital designers, products, and companies have been burned by this phenomenom. Rissacher EE365Lect #10

Back to the bistable…. How to control it? –Screwdriver –Control inputs S-R latch Rissacher EE365Lect #10

S-R latch operation Metastability is possible if S and R are negated simultaneously. (try it in Foundation) Rissacher EE365Lect #10

S-R latch timing parameters Propagation delay Minimum pulse width Rissacher EE365Lect #10

S-R latch symbols Rissacher EE365Lect #10

S-R latch using NAND gates Rissacher EE365Lect #10

S-R latch with enable Rissacher EE365Lect #10

D latch Rissacher EE365Lect #10

D-latch operation Rissacher EE365Lect #10

D-latch timing parameters Propagation delay (from C or D) Setup time (D before C edge) Hold time (D after C edge) Rissacher EE365Lect #10

Edge-triggered D flip-flop behavior Rissacher EE365Lect #10

D flip-flop timing parameters Propagation delay (from CLK) Setup time (D before CLK) Hold time (D after CLK) Rissacher EE365Lect #10

TTL edge-triggered D circuit Preset and clear inputs –like S-R latch 3 feedback loops –interesting analysis Light loading on D and C Rissacher EE365Lect #10

CMOS edge-triggered D circuit Two feedback loops (master and slave latches) Uses transmission gates in feedback loops Interesting analysis method (Sec. 7.9) Rissacher EE365Lect #10

Other D flip-flop variations Negative-edge triggered Clock enable Scan Rissacher EE365Lect #10

Scan flip-flops -- for testing TE = 0 ==> normal operation TE = 1 ==> test operation –All of the flip-flops are hooked together in a daisy chain from external test input TI. –Load up (“scan in”) a test pattern, do one normal operation, shift out (“scan out”) result on TO. Rissacher EE365Lect #10

J-K flip-flops Not used much anymore Rissacher EE365Lect #10

T flip-flops Important for counters Rissacher EE365Lect #10

In Class Practice Problem The characteristic Equation for a D latch is: Q* = D Write the Characteristic Equation for an S-R latch Rissacher EE365Lect #10

In Class Practice Problem The characteristic Equation for an S-R latch is: Q* = S + R’ Q Rissacher EE365Lect #10

In Class Practice Problem #2 Write characteristic equations for each of the following: J-K flip flop T flip flop T flip flop with enable Rissacher EE365Lect #10

In Class Practice Problem #2 Rissacher EE365Lect #10 J-K flip flop: T flip flop:

In Class Practice Problem #2 Write characteristic equations for each of the following: J-K flip flop –Q* = J Q’ + K’ Q T flip flop –Q* = Q’ T flip flop with enable –Q* = EN Q’ + EN’ Q Rissacher EE365Lect #10

SSI LATCHES and Flip-Flops Rissacher EE365Lect #10

Sequential PALs 16R8 Rissacher EE365Lect #10

One output of 16R8 8 product terms to D input of flip-flop –positive edge triggered, common clock for all Q output is fed back into AND array –needed for state machines and other applications Common 3-state enable for all output pins Rissacher EE365Lect #10

PAL16R6 Six registered outputs Two combinatio nal outputs (like the 16L8’s) Rissacher EE365Lect #10

GAL16V8 Each output is programmable as combinational or registered Also has programmable output polarity Rissacher EE365Lect #10

GAL16V8 output logic macrocell Rissacher EE365Lect #10

GAL22V10 More inputs More product terms More flexibility Rissacher EE365Lect #10

GAL22V10 output logic macrocell Rissacher EE365Lect #10

Next time State Machine Types State machine Design Rissacher EE365Lect #10