[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 06 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates (Refined)  Floorplanning (Refined)  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW (1bit) ARM (1bit) PED(1bit) CLK ARM1 [1:0] FSM Initial G.R Y.R R+L eft.R Y.R R.G R.Y R.R+L eft PED SW = 0 SW = 1 T < 2 T = 2 SW = 1 SW =0 T<10 PED = 1 T = 2 PED = 1 T = 2 T<= 2 SW = 0 T=15 T = 2 PED = 0 T = 2 PED = 0 ARM = 0ARM = 1 FSM For Lights Clear (1bit) ARM2 [1:0] PED(1bits) Blink T=10 T < 5 Complete(1bits)

Hold until n 1 or n 2 changes Light favors n 1 or n 2 ? n1n1 n2n2 T<r 1 ? T<r 2 ? T>= R 1 ?T>= R 2 ? n 1 =0? n 2 =0? f 1 <=0? f 2 <=0? Switch Light Reset T = 0 No Yes No Yes No Light favors arm 1 or arm 2 ? n1n1 n2n2 T<r left ? T>= R left ? No Yes No Yes No n 1 not change in T = 5? No Control reset Pedestrian For Green light For Red + Left T>= R p ? Yes No For Pedestrian n 2 not change in T = 5? n 1, n 2 :# of cars T :Time spent in this phase R i, r i : Max. and Min. time for each phase f i : the control function f 1 = α 1 *n 1 + β 1 – n 2 f 2 = α 2 *n 2 + β 2 – n 1

Block Diagram

Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

Block (# used)Transistor Counts Register ( 13 )6804 MUX ( 12 )9300 Accumulator ( 4 )1848 ALU ( 1 )4848 Comparator 8-bits ( 1 )240 Flow Control FSM832 Light Control FSM882 ROM~0 Other- Total24754 Transistor Counts Estimates

Block (# used)Transistor CountsSize Estimates (um) Register ( 13 ) MUX ( 12 ) Accumulator ( 4 ) ALU ( 1 ) Comparator 8-bits ( 1 ) Flow Control FSM Light Control FSM ROM~00 Other Total~ 24754~ Block Size Estimates

Register (1bit) 2X1 MUX Estimate Block Size From Layout : BlocksSize Estimates ( um ) 2:1 MUX (1bit) :1 MUX (1bit) :1 MUX (1bit) bit Register bit Register bit Register Accumulator (8-bit) = 34.4 x Accumulator (11-bit) = 47.3 x Light Control FSM * Flow Control FSM * ALU = x From equation, we obtain um^2 Comparator200 Asterisk(*) : no precise layout outline now. Some Basic Layout Ratio:

Transistor Counts T:154 X 2T:308 X 2 T:154 X 2T:308 X 2 T:132 X 2T:154 X 2 T: 96 X 8T:896 T:96T:154 T:112T:308 T:112T:308 T: 672 T: 96 T: 1540 X 2 T: 12 T: 1320 T: 1980 X 2 T: 1980 T: 1526T: 4848 T: 132 T: 240 T: 882T: 832

 M1, M2  Local connect  VSS & VDD  M3,M4  System Clock  Global Routing  Control Signals Metal Directionality

Question ?

User Input Q User Input R,r AccumReg 1 11 ENTER 11 AccumReg 11 OUT / LEFT s0,s1: X 2 q0,q1: X 2 Reg X Reg X 10 2:1 MUX X X 9 11 X 1 q0 q1 11 β n1 n0 11 Q_len11 16:1 MUX 4 Sel 11 s0 s111 Sel 4 N_avg αn 0 -n 1 αn 0 q 0 -s 0 q 1 -s 1 α0α0 α1α1 Q(αn 0 -n 1 ) ALU 2 Sel_ALU 1:16 De-MUX 4 Sel Reg X 9 12 bit Reg X1 11 bit n0 n1 ROM 11 β 2:1 MUX 12 n_avg Q(αn 0 -n 1 ) q 1 -s 1 q 0 -s 0 αn 0 αn 0 -n 1 11 F α 0,α 1: X 2 ROM Reg 8X X 8 : Dot Line to Comparator R,r, RL,rl for Arm1 Arm2 11 ½ 2:1 MUX Dot Lint to FSM β 8 X 8 2 : 1 MUX INT. Compar 1 FSM SW ARM CLK Clear FSM 1 Complete ARM 1 ARM 2 PED1 2 2 ½ 11 ROM 11 User Input 2:1 MUX Reg 11 Accmu 8 1 Clk Div. 8 Accmu 1 Left-Turn Counter T Reg System Clock 1 PED R & r, R_L& r_L Sel_C Ser_D 3 1 4X3 3 2 Sel_ALU Sel_C Sel ARM n 0 = 0 n 1 = 0 F <= 0 8 : 1 MUX n0n0 n1n1 F 1 Sel_D System Clock Trigger, when cars go left turn ARM Shifting 1