Binary-to-BCD Converter

Slides:

Advertisements

Similar presentations

UNIT 8: Synthesis Basics

Advertisements

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Arbitrary Waveform Discussion 5.5 Example 34.

Decoders Discussion D9.5 Example 25. Decoders 3-to-8 Decoder decoder38.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all;

Arithmetic Logic Unit (ALU)

Gray Code Converters Discussion D9.1 Example 16.

Shifters Discussion D7.1 Example Bit Shifter.

Divider Discussion D7.3 Example 20.

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Adder Discussion D6.2 Example 17. s i = c i ^ (a i ^ b i ) c i+1 = a i * b i + c i * (a i ^ b i ) Full Adder (Appendix I)

Binary-to-BCD Converter Lecture L6.2 Section 6.5 pp

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

Mridula Allani Spr 2011, Apr /6270 Guest Lecture by M. Allani.

Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

Single-Cycle Instructions VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM.

1 Comparators Discussion D A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin =

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

Structural VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T3: ALU Design.

Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Codes and Code Converters

Code Converters Module M7.1 Section 6.5. Code Converters Binary-to-BCD Converters ABEL TRUTH_TABLE Command.

Lab 2 4-Bit Adder Digilent Spartan 3 Board Lecture L2.3.

4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.

Sequencing and Control Mano and Kime Sections 8-1 – 8-7.

Logic Design Fundamentals - 2 Lecture L1.2. Logic Design Fundamentals - 2 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Decoders and Encoders Sections 3-5, 3-6 Mano & Kime.

Registers Lab 5 Mano and Kime Sections 5-2, 5-3, 5-7.

Arithmetic Logic Unit (ALU) Discussion D4.6. ALU N = negative flag (N=1 if y(n)=0 Z = zero flag (Z = 1 if Y = 0) V = overflow flag C = carry flag.

Binary-to-BCD Converter

4-Bit Binary-to-BCD Converter: case Statement

Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

Decoders and Encoders Discussion D4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

VHDL Examples Subra Ganesan Reference: Professor Haskell’s Notes,

4-bit Shift Register. 2-bit Register Serial-in-serial-out Shift Register.

Designing Combinational Logic Circuits in Verilog - 2

1 Part V: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

ECE 448: Spring 12 Lab Midterm Exam Review. Part 1: Detailed discussion of a selected midterm from Spring Part 2: Review & discussion of common.

Binary-to-BCD Converter

Figure 5.1 Conversion from decimal to binary. Table 5.1 Numbers in different systems.

Digital Systems Design VHDL simulation of a 3 – Bit Binary Decoder with Enable by Marc A. Mackey.

2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.

ECE 331 – Digital System Design Multi-bit Adder Circuits, Adder/Subtractor Circuit, and Multiplier Circuit (Lecture #12)

 Seattle Pacific University EE Logic System DesignCounters-1 Shift Registers DQ clk DQ DQ ShiftIn Q3Q3 Q2Q2 DQ Q1Q1 Q0Q0 A shift register shifts.

VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Number Representation and Arithmetic Circuits

Lecture 8 Review Combinational Devices –Decoder –Multiplexor (Bhasker p-81) –Shifter –Barrel Shifter (Bhasker p-303)

Multiplier: Functions Discussion D7.2 Example 19.

EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09.

Registers and Counters Discussion D8.1. Logic Design Fundamentals - 3 Registers Counters Shift Registers.

Instructor: Alexander Stoytchev CprE 281: Digital Logic.

Combinational logic circuit

UNIT 8: Synthesis Basics

Part III: SYSTEM DESIGN

Comparators Discussion DS-3.1.

BARREL SHIFTER.

Logic Design Review – 2 Basic Combinational Circuits

HDL Programming Fundamentals

Mano and Kime Sections 7-6 – 7-8

Analog-to-Digital Converters

Binary-to-BCD Converter

VHDL (VHSIC Hardware Description Language)

A Greatest Common Divisor (GCD) Processor

Fibonacci Sequence Lecture L4.1 Lab 3.

UNIT 6: Mixed-Type Description

High-Low Guessing Game

4-Input Gates VHDL for Loops

디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계

(Sequential-Circuit Building Blocks)

Presentation transcript:

Binary-to-BCD Converter Lab 2

Shift and Add-3 Algorithm 1. Shift the binary number left one bit. 2. If 8 shifts have taken place, the BCD number is in the Hundreds, Tens, and Units column. 3. If the binary value in any of the BCD columns is 5 or greater, add 3 to that value in that BCD column. 4. Go to 1.

Steps to convert an 8-bit binary number to BCD

Example of converting hex E to BCD

-- Title: Binary-to-BCD Converter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity binbcd is port ( B: in STD_LOGIC_VECTOR (7 downto 0); P: out STD_LOGIC_VECTOR (9 downto 0) ); end binbcd;

architecture binbcd_arch of binbcd is begin bcd1: process(B) variable z: STD_LOGIC_VECTOR (17 downto 0); for i in 0 to 17 loop z(i) := '0'; end loop; z(10 downto 3) := B; for i in 0 to 4 loop if z(11 downto 8) > 4 then z(11 downto 8) := z(11 downto 8) + 3; end if; if z(15 downto 12) > 4 then z(15 downto 12) := z(15 downto 12) + 3; z(17 downto 1) := z(16 downto 0); P <= z(17 downto 8); end process bcd1; end binbcd_arch;

16-bit Binary-to-BCD Converter

Verilog binbcd module binbcd(B,P); input [15:0] B; output [15:0] P; reg [15:0] P; reg [31:0] z; integer i;

always @(B) begin for(i = 0; i <= 31; i = i+1) z[i] = 0; z[18:3] = B; for(i = 0; i <= 12; i = i+1) if(z[19:16] > 4) z[19:16] = z[19:16] + 3; if(z[23:20] > 4) z[23:20] = z[23:20] + 3; if(z[27:24] > 4) z[27:24] = z[27:24] + 3; if(z[31:28] > 4) z[31:28] = z[31:28] + 3; z[31:1] = z[30:0]; end P = z[31:16]; endmodule