Chapter 13 Reduced Instruction Set Computers (RISC) CISC – Complex Instruction Set Computer RISC – Reduced Instruction Set Computer

Major Advances in Computers The family concept Microprogrammed control unit Cache memory Microprocessors Pipelining Multiple processors RISC processors

RISC Reduced Instruction Set Computer Key features —Large number of general purpose registers (or use of compiler technology to optimize register use) —Limited and simple instruction set —Emphasis on optimising the instruction pipeline

Comparison of processors

Driving force for CISC Software costs far exceed hardware costs Increasingly complex high level languages Semantic gap Leads to: —Large instruction sets —More addressing modes —Hardware implementations of HLL statements –e.g. CASE (switch) on VAX

Intention of CISC Ease compiler writing Improve execution efficiency —Complex operations in microcode Support more complex HLLs

Execution Characteristics Operations performed Operands used Execution sequencing Studies have been done based on programs written in HLLs Dynamic studies are measured during the execution of the program

Operations Assignments —Movement of data Conditional statements (IF, LOOP) —Sequence control Procedure call-return is very time consuming Some HLL instructions lead to many machine code operations

Weighted Relative Dynamic Frequency of HLL Operations [PATT82a] Dynamic Occurrence Machine-Instruction Weighted Memory-Reference Weighted PascalC C C ASSIGN45%38%13% 14%15% LOOP5%3%42%32%33%26% CALL15%12%31%33%44%45% IF29%43%11%21%7%13% GOTO—3%———— OTHER6%1%3%1%2%1%

Operands Mainly local scalar variables Optimization should concentrate on accessing local variables PascalCAverage Integer Constant16%23%20% Scalar Variable58%53%55% Array/Structure26%24%25%

Procedure Calls Very time consuming Depends on number of parameters passed Depends on level of nesting Most programs do not do a lot of calls followed by lots of returns Most variables are local

Implications – Characterize RISC Best support is given by optimising most used and most time consuming features —Large number of registers –Operand referencing —Careful design of pipelines –Branch prediction etc. —Simplified (reduced) instruction set

Register File Software solution —Require compiler to allocate registers —Allocate based on most used variables in a given time —Requires sophisticated program analysis Hardware solution —Have more registers —Thus more variables will be in registers

Registers for Local Variables Store local scalar variables in registers —Reduces memory access Every procedure (function) call changes locality —Parameters must be passed —Results must be returned —Variables from calling programs must be restored

Register Windows Only few local & Pass parameters Limited range of depth of call Use multiple small sets of registers Calls switch to a different set of registers Returns switch back to a previously used set of registers

Register Windows cont. Three areas within a register set —Parameter registers (Passed Parameters) —Local registers —Temporary registers (Passing Parameters) —Temporary registers from one set overlap parameter registers from the next —This allows parameter passing without moving data

Overlapping Register Windows

Circular Buffer diagram

Operation of Circular Buffer When a call is made, a current window pointer is moved to show the currently active register window If all windows are in use, an interrupt is generated and the oldest window (the one furthest back in the call nesting) is saved to memory A saved window pointer indicates where the next saved windows should restore to

Global Variables Allocated by the compiler to memory —Inefficient for frequently accessed variables Have a set of registers for global variables

Registers v Cache – which is better? Large Register FileCache All local scalarsRecently-used local scalars Individual variablesBlocks of memory Compiler-assigned global variablesRecently-used global variables Save/Restore based on procedure nesting depthSave/Restore based on cache replacement algorithm Register addressingMemory addressing

Referencing a Scalar - Window Based Register File

Referencing a Scalar - Cache

Compiler Based Register Optimization Assume relativelysmall number of registers (16-32) Optimizing the use is up to compiler HLL programs have no explicit references to registers Process: Assign symbolic or virtual register to each candidate variable Map (unlimited) symbolic registers to (limited) real registers Symbolic registers that do not overlap can share real registers If you run out of real registers some variables use memory

Graph Coloring Given a graph of nodes and edges Nodes are symbolic registers Two symbolic registers that are live in the same program fragment are joined by an edge Assign a color to each node Adjacent nodes must have different colors Use minimum number of colors Try to color the graph with n colors, where n is the number of real registers Nodes that can not be colored are placed in memory

Graph Coloring Application

Why CISC (1)? Compiler simplification? —Dispute… - Complex machine instructions harder to exploit - Optimization actually may be more difficult Smaller programs? (Memory is now cheap) —Programs may take up less instructions, but… —May not occupy less memory, just look shorter in symbolic form –More instructions require longer op-codes, memory references –Register references require fewer bits

Why CISC (2)? Faster programs? —More complex control unit —Microprogram control store larger —> Thus instructions take longer to execute Bias towards use of simpler instructions ? It is far from clear that CISC is the appropriate solution

RISC Characteristics One instruction per cycle Register to register operations Few, simple addressing modes Few, simple instruction formats Also Hardwired design (no microcode) Fixed instruction format But More compile time/effort

Classical RISC Characteristics

RISC v CISC Not clear cut Many designs borrow from both philosophies

Memory to memory vs Register to memory Operations

Characteristics of Example Processors

More Options of Architectures RISC Pipelining —Superscaler – replicates stages of pipeline —Superpipelined – fine grain pipeline

RISC Pipelining basics Two phases of execution —I: Instruction fetch —E: Execute –ALU operation with register input and output For load and store —I: Instruction fetch —E: Execute –Calculate memory address —D: Memory –Register to memory or memory to register operation

Effects of Pipelining

Optimization of Pipelining Delayed branch —Does not take effect until after execution of following instruction —This, following instruction is the delay slot

Normal and Delayed Branch

Use of Delayed Branch

Early RISC Computers MIPS – Microprocessor without Interlocked Pipeline Stages Stanford (John Hennessy) MIPS Technology SPARC – Scalable Processor Architecture Berkeley (David Patterson) Sun Microsystems 801 – IBM Research (George Radin )

Controversy: CISC vs RISC Problems —No pair of RISC and CISC that are directly comparable —No definitive set of test programs —Difficult to separate hardware effects from complier effects —Most comparisons done on “toy” rather than production machines —Most commercial devices are a mixture