Digital CMOS Logic Circuits

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Presentation transcript:

Digital CMOS Logic Circuits 1

sedr42021_1001.jpg Figure 10.1 Digital IC technologies and logic-circuit families.

sedr42021_1002.jpg Figure 10.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

sedr42021_1003.jpg Figure 10.3 Definitions of propagation delays and switching times of the logic inverter.

sedr42021_1004.jpg Figure 10.4 (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion.

sedr42021_1005.jpg Figure 10.5 The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched.

sedr42021_1006.jpg Figure 10.6 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving an identical inverter formed by Q3 and Q4.

sedr42021_1007a.jpg Figure 10.7 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.

sedr42021_1008.jpg Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.

sedr42021_1009a.jpg Figure 10.9 Examples of pull-down networks.

sedr42021_1010a.jpg Figure 10.10 Examples of pull-up networks.

sedr42021_1011a.jpg Figure 10.11 Usual and alternative circuit symbols for MOSFETs.

sedr42021_1012.jpg Figure 10.12 A two-input CMOS NOR gate.

sedr42021_1013.jpg Figure 10.13 A two-input CMOS NAND gate.

sedr42021_1014.jpg Figure 10.14 CMOS realization of a complex gate.

sedr42021_1015a.jpg Figure 10.15 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (10.25). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (10.26). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 10.27).

sedr42021_1016.jpg Figure 10.16 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.

sedr42021_1017.jpg Figure 10.17 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of QN and QP, respectively, of the basic inverter.

sedr42021_1018.jpg Figure 10.18 Circuit for Example 10.2.

sedr42021_1019a.jpg Figure 10.19 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load NMOS inverter. (c) The depletion-load NMOS inverter.

sedr42021_1020.jpg Figure 10.20 Graphical construction to determine the VTC of the inverter in Fig. 10.19.

sedr42021_1021.jpg Figure 10.21 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V, Vtn = –Vtp = 1 V, and r = 9.

sedr42021_1022a.jpg Figure 10.22 NOR and NAND gates of the pseudo-NMOS type.

sedr42021_1023a.jpg Figure 10.23 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).

sedr42021_1024a.jpg Figure 10.24 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.

sedr42021_1025a.jpg Figure 10.25 A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in (b) through switch S2.

sedr42021_1026.jpg Figure 10.26 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed (vC is high) and the input going high (vI = VDD).

sedr42021_1027.jpg Figure 10.27 Operation of the NMOS switch as the input goes low (vI = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles comparison to the circuit in Fig. 10.26.

sedr42021_1028.jpg Figure 10.28 The use of transistor QR, connected in a feedback loop around the CMOS inverter, to restore the VOH level, produced by Q1, to VDD.

sedr42021_1029a.jpg Figure 10.29 Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.

sedr42021_1030.jpg Figure 10.30 Realization of a two-to-one multiplexer using pass-transistor logic.

sedr42021_1031.jpg Figure 10.31 Realization of the XOR function using pass-transistor logic.

sedr42021_1032.jpg Figure 10.32 An example of a pass-transistor logic gate utilizing both the input variables and their complements. This type of circuit is therefore known as complementary pass-transistor logic or CPL. Note that both the output function and its complement are generated.

sedr42021_1033a.jpg Figure 10.33 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.

sedr42021_1034a.jpg Figure 10.34 (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge-sharing problem at the expense of static power dissipation.

sedr42021_1035.jpg Figure 10.35 Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase CL2 will partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction.

sedr42021_e1012.jpg Figure E10.12

Figure 10. 36 The Domino CMOS logic gate Figure 10.36 The Domino CMOS logic gate. The circuit consists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to VDD).

sedr42021_1037a.jpg Figure 10.37 (a) Two single-input domino CMOS logic gates connected in cascade. (b) Waveforms during the evaluation phase.

sedr42021_1038.jpg Figure 10.38 Capture schematic of the CMOS inverter in Example 10.5.

sedr42021_1039.jpg Figure 10.39 Input–output voltage transfer characteristic (VTC) of the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.

sedr42021_1040a.jpg Figure 10.40 (a) Output voltage, and (b) supply current versus input voltage for the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.

sedr42021_1041.jpg Figure 10.41 Transient response of the CMOS inverter in Example 10.5 with mp/mn = 1 and mp/mn = 4.

sedr42021_p1014.jpg Figure P10.14

sedr42021_p1036a.jpg Figure P10.36

sedr42021_p1038a.jpg Figure P10.38

sedr42021_p1049a.jpg Figure P10.49

sedr42021_p1051.jpg Figure P10.51