Data Dependencies A dependency type that can cause a stall.

Slides:



Advertisements
Similar presentations
Compiler Support for Superscalar Processors. Loop Unrolling Assumption: Standard five stage pipeline Empty cycles between instructions before the result.
Advertisements

Software Exploits for ILP We have already looked at compiler scheduling to support ILP – Altering code to reduce stalls – Loop unrolling and scheduling.
ILP: IntroductionCSCE430/830 Instruction-level parallelism: Introduction CSCE430/830 Computer Architecture Lecturer: Prof. Hong Jiang Courtesy of Yifeng.
Instruction-Level Parallel Processors {Objective: executing two or more instructions in parallel} 4.1 Evolution and overview of ILP-processors 4.2 Dependencies.
Computer Architecture Lecture 3 – Part 2 15 th May, 2006 Abhinav Agarwal Veeramani V.
COMP381 by M. Hamdi 1 (Recap) Pipeline Hazards. COMP381 by M. Hamdi 2 I n s t r. O r d e r add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11.
1 Pipelining Part 2 CS Data Hazards Data hazards occur when the pipeline changes the order of read/write accesses to operands that differs from.
Carnegie Mellon Lecture 7 Instruction Scheduling I. Basic Block Scheduling II.Global Scheduling (for Non-Numeric Code) Reading: Chapter 10.3 – 10.4 M.
Compiler techniques for exposing ILP
FTC.W99 1 Advanced Pipelining and Instruction Level Parallelism (ILP) ILP: Overlap execution of unrelated instructions gcc 17% control transfer –5 instructions.
COMP4611 Tutorial 6 Instruction Level Parallelism
Advanced Pipelining Optimally Scheduling Code Optimally Programming Code Scheduling for Superscalars (6.9) Exceptions (5.6, 6.8)
Pipeline Optimization
Data Dependence Types and Associated Pipeline Hazards Chapter 4 — The Processor — 1 Sections 4.7.
Anshul Kumar, CSE IITD CS718 : VLIW - Software Driven ILP Introduction 23rd Mar, 2006.
Eliminating Stalls Using Compiler Support. Instruction Level Parallelism gcc 17% control transfer –5 instructions + 1 branch –Reordering among 5 instructions.
EECC551 - Shaaban #1 Fall 2003 lec# Pipelining and Exploiting Instruction-Level Parallelism (ILP) Pipelining increases performance by overlapping.
EEL Advanced Pipelining and Instruction Level Parallelism Lotzi Bölöni.
1 Advanced Computer Architecture Limits to ILP Lecture 3.
Chapter 4 Advanced Pipelining and Intruction-Level Parallelism Computer Architecture A Quantitative Approach John L Hennessy & David A Patterson 2 nd Edition,
Pipeline Computer Organization II 1 Hazards Situations that prevent starting the next instruction in the next cycle Structural hazards – A required resource.
Lecture Objectives: 1)Define pipelining 2)Calculate the speedup achieved by pipelining for a given number of instructions. 3)Define how pipelining improves.
Instruction Level Parallelism (ILP) Colin Stevens.
1 Lecture 4: Advanced Pipelines Data hazards, control hazards, multi-cycle in-order pipelines (Appendix A.4-A.10)
EECC551 - Shaaban #1 Winter 2002 lec# Pipelining and Exploiting Instruction-Level Parallelism (ILP) Pipelining increases performance by overlapping.
EECC551 - Shaaban #1 Spring 2006 lec# Pipelining and Instruction-Level Parallelism. Definition of basic instruction block Increasing Instruction-Level.
EECC551 - Shaaban #1 Fall 2005 lec# Pipelining and Instruction-Level Parallelism. Definition of basic instruction block Increasing Instruction-Level.
1  2004 Morgan Kaufmann Publishers Chapter Six. 2  2004 Morgan Kaufmann Publishers Pipelining The laundry analogy.
Chapter 2 Instruction-Level Parallelism and Its Exploitation
CSCE 212 Quiz 9 – 3/30/11 1.What is the clock cycle time based on for single-cycle and for pipelining? 2.What two actions can be done to resolve data hazards?
EECC551 - Shaaban #1 Winter 2011 lec# Pipelining and Instruction-Level Parallelism (ILP). Definition of basic instruction block Increasing Instruction-Level.
EECC551 - Shaaban #1 Spring 2004 lec# Definition of basic instruction blocks Increasing Instruction-Level Parallelism & Size of Basic Blocks.
1 Lecture 4: Advanced Pipelines Control hazards, multi-cycle in-order pipelines, static ILP (Appendix A.4-A.10, Sections )
In-Order Execution In-order execution does not always give the best performance on superscalar machines.  The following example uses in-order execution.
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Instruction Level Parallelism Pipeline with data forwarding and accelerated branch Loop Unrolling Multiple Issue -- Multiple functional Units Static vs.
CA406 Computer Architecture Pipelines... continued.
5/13/99 Ashish Sabharwal1 Pipelining and Hazards n Hazards occur because –Don’t have enough resources (ALU’s, memory,…) Structural Hazard –Need a value.
Introduction to Computer Organization Pipelining.
L17 – Pipeline Issues 1 Comp 411 – Fall /23/09 CPU Pipelining Issues Read Chapter This pipe stuff makes my head hurt! What have you been.
Advanced Pipelining 7.1 – 7.5. Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike.
IBM System 360. Common architecture for a set of machines
CDA3101 Recitation Section 8
Computer Architecture Principles Dr. Mike Frank
/ Computer Architecture and Design
CS203 – Advanced Computer Architecture
Single Clock Datapath With Control
CDA 3101 Spring 2016 Introduction to Computer Organization
Computer Architecture Lecture 3 – Part 1 11th May, 2006
Computer Architecture Lecture 3
Computer Architecture
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Instruction Level Parallelism (ILP)
Data Hazard Example (stall).
Project Instruction Scheduler Assembler for DLX
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Instruction Rescheduling and Loop-Unroll
pipelining: data hazards Prof. Eric Rotenberg
Reducing pipeline hazards – three techniques
Prof. Sirer CS 316 Cornell University
CSC3050 – Computer Architecture
Dynamic Hardware Prediction
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Appendix C Practice Problem Set 1
Data Hazard Example (no stalls).
How to improve (decrease) CPI
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Pipelining and Exploiting Instruction-Level Parallelism (ILP)
Presentation transcript:

Data Dependencies A dependency type that can cause a stall.

Data Dependencies A dependency type that can cause a stall. RAW – Read After Write

Data Dependencies A dependency that causes a stall.

Data Dependencies A dependency that causes a stall. Hazard

Data Dependencies A technique for removing WAW and WAR dependencies

Data Dependencies A technique for removing WAW and WAR dependencies Register Renaming

Data Dependencies A software technique for reducing RAW hazards

Data Dependencies A software technique for reducing RAW hazards Instruction Reordering Loop Unrolling

Data Dependencies A hardware technique for reducing RAW hazards

Data Dependencies A hardware technique for reducing RAW hazards Data Forwarding Out of order execution

Data Dependencies The type of dependency between these two instructions: lw $1, 0($2) sw $1, 0($3)

Data Dependencies The type of dependency between these two instructions: lw $1, 0($2) sw $1, 0($3) RAW

Data Dependencies The reason WAW and WAR dependencies hurt performance

Data Dependencies The reason WAW and WAR dependencies hurt performance They limit instruction reordering

Data Dependencies Limiting factor in hardware register renaming

Data Dependencies Limiting factor in hardware register renaming Number of physical registers

Data Dependencies Limiting factor in software register renaming

Data Dependencies Limiting factor in hardware register renaming Number of architected registers (registers in ISA or assembly)