CS61C L26 CPU Design : Designing a Single-Cycle CPU II (1) Garcia, Spring 2010 © UCB inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 26 CPU Design: Designing a Single-cycle CPU, pt Apple to end AT&T monopoly?  The Wall Street Journal reports that Apple is developing a CDMA cell phone that could be used by Verizon and Sprint. Most carriers (incl AT&T) use GSM. Lots of people declining to comment, but if there’s any truth to this, it’s great! Lecturer SOE Dan Garcia apple.com/iphone Hello to Vinay Kumar listening from Columbia Univ!

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (2) Garcia, Spring 2010 © UCB How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) => datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (3) Garcia, Spring 2010 © UCB Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay “Critical path” (longest path through logic) determines length of clock period Clk

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (4) Garcia, Spring 2010 © UCB Register-Register Timing: One complete cycle Clk PC Rs, Rt, Rd, Op, Func ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (5) Garcia, Spring 2010 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] oprsrtimmediate bits16 bits5 bits immediate bits ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 Rd But we’re writing to Rt register??

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (6) Garcia, Spring 2010 © UCB 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] oprsrtimmediate bits16 bits5 bits immediate bits Already defined 32-bit MUX; Zero Ext? What about Rt register read?? 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc ALU 5 RegDst

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (7) Garcia, Spring 2010 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd ZeroExt 3216 imm16 ALUSrc ALU 5 RegDst

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (8) Garcia, Spring 2010 © UCB 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5 ?

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (9) Garcia, Spring 2010 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (10) Garcia, Spring 2010 © UCB 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrc ExtOp MemtoReg clk Data In 32 MemWr ALU 0 1 WrEnAdr Data Memory 5

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (11) Garcia, Spring 2010 © UCB 3f: The Branch Instruction beq rs, rt, imm16 mem[PC] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction’s address  PC = PC ( SignExt(imm16) x 4 ) else  PC = PC + 4 oprsrtimmediate bits16 bits5 bits

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (12) Garcia, Spring 2010 © UCB Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate bits16 bits5 bits Already have mux, adder, need special sign extender for PC, need equal compare (sub?) imm16 clk PC 00 4 nPC_sel PC Ext Adder Mux Inst Address 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile RsRt ALU 5 = Equal

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (13) Garcia, Spring 2010 © UCB Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr Equal Instruction Imm16RdRtRs clk PC 00 4 nPC_sel PC Ext Adr Inst Memory Adder Mux = ALU 0 1 WrEnAdr Data Memory 5

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (14) Garcia, Spring 2010 © UCB An Abstract View of the Implementation Data Out clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions clk ALU

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (15) Garcia, Spring 2010 © UCB An Abstract View of the Critical Path Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write clk 5 RwRaRb Register File Rd Data In Data Addr Ideal Data Memory Instruction Address Ideal Instruction Memory PC 5 Rs 5 Rt 32 A B Next Address clk ALU (Assumes a fast controller)

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (16) Garcia, Spring 2010 © UCB Administrivia Any administrivia to announce?

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (17) Garcia, Spring 2010 © UCB Peer Instruction 1)In the worst case, the biggest delay is the memory access time 2)With only changes to control, our datapath could write to memory and registers in one cycle. 12 a) FF b) FT c) TF d) TT

CS61C L26 CPU Design : Designing a Single-Cycle CPU II (18) Garcia, Spring 2010 © UCB Summary: A Single Cycle Datapath 32 ALUctr clk busW RegWr 32 busA 32 busB 55 RwRaRb RegFile Rs Rt Rd RegDst Extender 3216 imm16 ALUSrcExtOp MemtoReg clk Data In 32 MemWr zero = ALU 0 1 WrEnAdr Data Memory 5 Instruction Imm16RdRtRs nPC_sel instr fetch unit clk We have everything except control signals