Bachelor of Applied Science Thesis Defense An Analysis of Network-on-Chip Implementations on Field Programmable Gate Arrays Kevan Thompson Computer Engineering School of Engineering Science, SFU

Overview  Introduction  Background  Methodology  Results  Conclusions and Future Work

Introduction Virtex-7 Virtex-6 Virtex-5 Virtex-4

ASIC Vs FPGA ASIC:  Completely Custom Design  Large Initial Investment  Need to carefully design interconnect between nodes FPGA:  Reconfigurable  Low cost for small volume runs  Wires already placed on the FPGA

Objective  Improvements in the Xilinx tools that have significantly affected the performance of NoCs on FPGAs  Improvements in NoC performance on FPGAs that are possible using manual PAR  The Star and Fully Connected topologies do not fit into current models

NoC Terminology Topology Node Degree Average Node Degree (AND)

Previous Work on NoCs on FPGAs For Xilinx FPGAs:

Methodology  8-bit multiplier node  Two Fast Simplex Links (FSLs)  Network topology communication switch  FSLs: 16-word-deep queues,24-bit width  Multiplier uses 981 Flip-flops, and 653 LUTs  FPGA Xilinx Virtex-5 xc5vlx330

Results  10.1 Tools Vs 12.1 Tools Star, Ring, and Fully Connected Networks  Predicted Vs Measured Results Star, and Fully Connected Networks  Manual Implementation  Ring, Star, and Mesh Networks

10.1 Tools VS 12.1 Tools for Star Networks

10.1 Tools VS 12.1 Tools for Ring Networks

10.1 Tools VS 12.1 Tools for Fully Connected Networks

Percent Improvement of 12.1 Tools Over 10.1 Tools

Star Networks

Results

Results for Adjusted Model

Comparison of Models

Prediction of Adjusted Model for Random Networks

Fully Connected Networks

Results

CAD Tool Synthesis Steps  HDL is parsed for recognizable constructs  Constructs mapped to the specific FPGAs technology  Components of the design are placed on the FPGA using Simulated Annealing  Wires are connected between the components, using an algorithm called Pathfinder

Automatic PAR of a 96 node Ring Network

Manual PAR of a 96 Node Ring Network

Ring Network Pre and Post PlanAhead Results

Star Network Pre and Post PlanAhead Results

Mesh Network Pre and Post PlanAhead Results

Conclusions  Xilinx 12.1 Tools offer significant improvements in the PAR of NoCs on FPGAs  The analytical model proposed by Lee et al[1] does accuratly predict the performance of Star, and Fully Connected Networks  Using manual PAR it is possible to improve the performance of NoCs on FPGAs

Future Work  Compare the performance of the Xilinx 10.1 tools suite and the Xilinx 12.1 tools suite for link widths of 16, and 32 bits  Build Star and Fully Connected networks with link widths of 16, and 32 bits  Create manual implementations for Torus and Hyper Cube topologies

Acknowledgements  Dr. Lesley Shannon  Dr. Ash Parameswaran  Michael Sjoerdsma  Viewers Like you!

References [1] J. Lee. “An Analytical Model Describing The Performance Of Application-Specific Networks-On-Chip On Field-Programmable Gate Arrays” M.A.Sc. thesis, Simon Fraser University, Canada, [2] Xilinx. “Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet” Available: [3] Xilinx. “Virtex-4 Family Overview” Available: [4] Xilinx. “Virtex-5 Family Overview” Available: [5] Xilinx. “Virtex-6 Family Overview” Available: [6] Xilinx. “Virtex-7 Product Table” Available: [7] Xilinx. “What's New in Xilinx ISE Design Suite 12” Available: htm# htm#121

References Cont… [8] Cisco Systems Inc. “Fiber Distributed Data Interface” Available: [9] Cisco Systems Inc. “Token Ring/IEEE 802.5” Available: [10] Cisco Systems Inc. “Ethernet Technologies” Available: [11] Kompics. “Distributed System Launcher” Available: [12] T. Kranenburg, R. van Leuken. “MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture”, DATE, France, [13] K Eguro, S. Hauck, A. Sharma. “Architecture -Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement”, DAC, United States, [14] G. Grewal, M. O’Cleirigh, M. Wineberg. “An Evolutionary Approach to Behavioral-Level Synthesis”, CEC, Australia,

References Cont… [15] C Legl, B Wurth, K. Eckl. “A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs”, DAC, United States, [16]S Chin, S Wilton. “An Analytical Model Relating Fpga Architecture And Place And Route Runtime”, FPL, Czech Republic, [17]R Gindin, I Cidon, I Keidar. “NoC-Based FPGA: Architecture and Routing”, NOCS, United States, 2007.

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