Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 101 Lecture 10 Combinational ATPG and Logic Redundancy n Redundancy identification n Redundancy removal.

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Presentation transcript:

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 101 Lecture 10 Combinational ATPG and Logic Redundancy n Redundancy identification n Redundancy removal

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 102 Irredundant Hardware and Test Patterns n Combinational ATPG cannot always find redundant (unnecessary) hardware n Fault Test a sa1, b sa0 A = 1 a sa0, b sa1 A = 0 n Therefore, these faults are not redundant

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 103 Redundant Hardware and Simplification

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 104 Redundant Fault q sa1

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 105 Multiple Fault Masking n Single fault f sa0 is tested by input vector 110.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 106 Multiple Fault Masking n f sa0 is masked when fault q sa1 is also present.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 107 Intentional Redundant Implicant BC n Elimination of hazards in circuit output

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 108 Fault Cone and D-frontier n Fault Cone – Set of hardware affected by fault n D-frontier – Set of gates closest to POs with fault effect(s) at input(s) Fault Cone D-frontier

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 109 Algorithm 7.1 (p. 171) Redundancy Removal Repeat until there are no redundant faults: { Use ATPG to find all redundant faults; Remove all redundant faults with non- overlapping fault cone areas; }

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