Final Presentation: April 25 th, 2005 Seri Abd Rauf Fatima Boujarwah Juan Chen Liyana Sharipp Arti Thumar : Integrated Circuit Design Project, Spring 2005 Project Manager: Bobby Colyer Overall Design Goal: Implementing Noise Canceling Algorithm in Hardware

18-525: Integrated Circuit Design Project, Spring 2005 Got an iPod? Can you hear the noise? Want to know why? Cell phone? Car? PDA? No?

Most devices that we use throughout the day have a noise canceling component –Audio –Visual –Motion : Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layout 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

Also known as the Intelligent Microsurgical Instrument Project A research done here at CMU, led by Prof Riviere and Dean Khosla Project Goal: To enhance accuracy in microsurgery Problem Definition: Physiological Tremor Non-tremulous errors Method Weighted Fourier Linear Combiner (WFLC) for noise canceling purposes How does this help solve the problems?

WFLC Revised Flow ChartOriginal Flow Chart : Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

Microsurgical InstrumentsHuman-Computer Interfaces Vehicle ManeuveringHearing Aid

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

Goal: To minimize noise Algorithm: Based on adaptive filtering depending on signal weights Pseudo-code: i)Take the input signal and model it using Fourier Transform ii)For each sample, model it by approximating the weight constant and feeding it back to the next sample iii)Each sample model is then subtracted from the original input signal to monitor the error

Output w1 + - Sin(sumw0) Integration Block Integrator Block Cos(sumw0)w2 Input LMS w0 Error Generate Adaptive Weights to Calculate Output Take Fourier Transform of Input Signal using previous Error Sample Output Subtracted from Input Signal to Generate Current Error Repeat the Process for the next Sample Input

counter ROM Sine Converter Cosine Converter FPMult 1 FPMult FPAdd FPAdd/Sub Datum Offset w1 Out FPSub e AddOne w2 mu FPMult : Integrated Circuit Design Project, Spring 2005

The BIG Picture Marketing Potential Behavioral/ Algorithm Description Design Process Floorplan Evolution Layouts Verification Challenges Chip Specifications Finale : Integrated Circuit Design Project, Spring 2005

Floating Point Multipliers Array vs Wallace tree structures for power saving : Integrated Circuit Design Project, Spring 2005

Wallace + Booth vs Wallace for better layout design –saved 2K transistors –inserted smaller modules in top level to fill up the white space Buffered each bit of the output : Integrated Circuit Design Project, Spring 2005

Floating Point Adders Ripple Carry Adder vs. Carry Look-ahead Adder Mirror Adder vs. Mux-based Adder Mirror AdderMux-based Adder # of transistors2418 Area11.52 x x 5.62 Output signalStableUnstable : Integrated Circuit Design Project, Spring 2005

Changed the general FPAdd/Sub (with input signal ‘sub’) for all the three adders to: –FPAdd for the top adder –FPSub for the middle adder –FPAddSub for the bottom adder Barrel shifter vs. Logarithmic shifter –Barrel shifter is used during normalizing – consumes less power –Log shifter is used during denormalizing – easier to extract the sticky bits Changed Ripple Borrow Subtractor to Ripple Carry Adder with Carry In = 1 Eliminate ‘sub’ and minimize the logic for sign bit : Integrated Circuit Design Project, Spring 2005

MUX and Register Designed MUXes based on where the inputs and outputs are in the top level floorplan Designed registers based on their functionalities and inputs/outputs positions –Mu, Offset, Datum: Negative Edge Triggered DFF –w1, w2, Out, e : Clear-Alternate Enabled DFF : Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

5 Floating Point Adders?

18-525: Integrated Circuit Design Project, Spring 2005 Need better routing channels Need to redesign muxes to avoid congestions Move this there…

18-525: Integrated Circuit Design Project, Spring 2005 And we thought this would be our final floorplan…

18-525: Integrated Circuit Design Project, Spring 2005 The multipliers turned out to be smaller!

18-525: Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

Denormalizing Normalizing Output Logic Add/Sub

18-525: Integrated Circuit Design Project, Spring 2005

Rounding Unit Wallace Tree Multiplier

18-525: Integrated Circuit Design Project, Spring 2005

Alternator Buffers : Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

*Test Files are from Robot Assisted Needle Insertion Research Conducted by Professor Cameron Riviere These inputs approximate to: Constants: MU = 0.1 OFFSET = 10 Inputs: DATUM = : Integrated Circuit Design Project, Spring 2005

Behavioral resultsStructural results Output Error Similar Plots: Slight Differences due to 16-bit Floating Point Units : Integrated Circuit Design Project, Spring 2005

**First three test vectors verify correctness of the layout Output Bits 0-7: Clean Output Signals: 1.8V : Integrated Circuit Design Project, Spring 2005

The BIG Picture Marketing Potential Behavioral/ Algorithm Description Design Process Floorplan Evolution Layouts Verification Challenges Chip Specifications Finale : Integrated Circuit Design Project, Spring 2005

Transistor Count –Solution: Reused hardware Hardware Sharing –Caused timing issue –Split the circuit into two cycles Sufficient Signal Strength –Improved Vdd and Gnd rail connections –Buffering techniques

The BIG Picture Marketing Potential Behavioral/ Algorithm Description Design Process Floorplan Evolution Layouts Verification Challenges Chip Specifications Finale : Integrated Circuit Design Project, Spring 2005

Size of Design µm x µm Aspect Ratio1:1.21 Transistor Count25385 Density0.232 transistors/µ 2 Clock Frequency50KHz Power2.507mW Pin Count84 pins : Integrated Circuit Design Project, Spring 2005

Vdd! Gnd! In/Out Datum Mu Offset Clk Reset In Out e Out Total # of Pins: : Integrated Circuit Design Project, Spring 2005

1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale : Integrated Circuit Design Project, Spring 2005

We will never be the same… Everyone must have a cell phone with a good noise canceling function Shopping is not a priority anymore. Metal 3 is not ‘in’ this season The early bird gets the worm…but can we get up? (hmmm, did we ever get to sleep? The Butterfly effect applies to EVERYTHING, including…floorplannig

18-525: Integrated Circuit Design Project, Spring 2005

There are hundreds of applications for noise cancellation devices in our everyday lives Such algorithms are crucial in improving the quality of lives of many people : Integrated Circuit Design Project, Spring 2005 So, in conclusion, our chip:  Is universally effective and efficient in canceling noise  Can be used to cancel all types of noise  Will save lives

C. N. Riviere, “Predicting Respiratory Motion for Active Canceling During Percutaneous Needle Insertion”, Oct : Integrated Circuit Design Project, Spring 2005