Registers Lab 5 Mano and Kime Sections 5-2, 5-3, 5-7

4-Bit Register

library IEEE; use IEEE.std_logic_1164.all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) ); end reg; A Generic Register

architecture reg_arch of reg is begin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end process; end reg_arch; Infers a flip-flop for all outputs (q)

debounce entity entity debounce is port ( inp, clk, clr: in std_logic; outp: out std_logic ); end debounce; debounce inpoutp clk clr

clk inp delay1 delay3 delay2 outp debounce

clk inp delay1 delay3 delay2 outp

architecture rtl of debounce is signal delay1, delay2, delay3: std_logic; begin process(clk, clr) begin if clr = '1' then delay1 <= '0'; delay2 <= '0'; delay3 <= '0'; elsif clk'event and clk='1' then delay1 <= inp; delay2 <= delay1; delay3 <= delay2; end if; end process; outp <= delay1 and delay2 and (not delay3); end rtl; debounce architecture

Lab 5 – A Single-Cycle Processor

fcode (hex) Namey 10+ b + a 11- b - a 121+ a a INVERT Complement all bits of a. 15AND b and a 16OR b or a 17XOR b xor a 182* Logic shift left a. 19U2/ Logic shift right a. 1A2/ Arithmetic shift right a. 1BRSHIFT Shift b a bits to the right. SHR(b,a); 1CLSHIFT Shift b a bits to the left. SHL(b,a); 1D Reserved for multiplication 1E Reserved for division Add:

20TRUE Set all bits in a to ‘1’. 21FALSE Clear all bits in a to ‘0’. 22NOT 0= TRUE if all bits in a are ‘0’. 230< TRUE if sign bit of a is ‘1’. 24U> TRUE if b > a (unsigned), else FALSE 25U< TRUE if b < a (unsigned), else FALSE 26= TRUE if b = a, else FALSE 27U>= TRUE if b >= a (unsigned), else FALSE 28U<= TRUE if b <= a (unsigned), else FALSE 29<> TRUE if b /= a, else FALSE 2A> TRUE if b > a (signed), else FALSE 2B< TRUE if b < a (signed), else FALSE 2C>= TRUE if b >= a (signed), else FALSE 2D<= TRUE if b <= a (signed), else FALSE fcode (hex) Namey Add:

clk_pulse.vhd

Pcount.vhd -- A 4-bit up-counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Pcount is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (3 downto 0) ); end Pcount;

architecture Pcount_arch of Pcount is signal COUNT: STD_LOGIC_VECTOR (3 downto 0); begin process (clk, clr) begin if clr = '1' then COUNT <= "0000"; elsif clk'event and clk='1' then COUNT <= COUNT + 1; end if; q <= COUNT; end process; end Pcount_arch; Pcount.vhd (cont.)

dig7seg.vhd

Prom Single-cycle microcoded instructions InstructionOperation DUP Duplicate T to N. SWAP Swap the contents of T and N Load the 8-bit byte from SW(1:8) into T and push T to N Additional Instructions

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity Prom is port ( addr: in STD_LOGIC_VECTOR (3 downto 0); M: out STD_LOGIC_VECTOR (8 downto 0) ); end Prom; Prom.vhd

architecture Prom_arch of Prom is constant dup: STD_LOGIC_VECTOR (9 downto 0) := " "; constant swap: STD_LOGIC_VECTOR (9 downto 0) := " "; constant Sfetch: STD_LOGIC_VECTOR (9 downto 0) := " "; constant plus: STD_LOGIC_VECTOR (9 downto 0) := " "; constant oneplus: STD_LOGIC_VECTOR (9 downto 0) := " "; constant invert: STD_LOGIC_VECTOR (9 downto 0) := " "; constant orr: STD_LOGIC_VECTOR (9 downto 0) := " "; constant twotimes: STD_LOGIC_VECTOR (9 downto 0) := " "; constant lshift: STD_LOGIC_VECTOR (9 downto 0) := " " Prom.vhd

Lab 5 – A Single-Cycle Processor

Lab5.whp HEX lshift\ or\ *\ D26E D26E 00A4 +\ D312 invert\ 2CED 1+\ 2CEE

subtype rom_word is std_logic_vector(9 downto 0); type rom_array is array (NATURAL range <>) of rom_word); constant rom: rom_array := ( Sfetch, -- then set switches to 08 hex Sfetch, lshift, Sfetch, orr, twotimes, Sfetch, plus, invert, oneplus, X”0000”, X”0000” ); begin process(addr) variable j: integer; begin j := conv_integer(addr); M <= rom(j); end process; end Prom_arch; Prom.vhd (cont.)