From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved. 7.2 A Central Processor Centralization approach –As much functionality as possible was collected Decentralized approach –The system contains multiple processors

7.3 CPU Complexity Why is a CPU so complex ? –Multiple roles –Protection and privilege –Hardware priorities –Generality –Data size –High speed

7.4 Modes of Execution The features usually associated –The subset of instructions that are valid –The size of data items –The region of memory that can be accessed –The functional units that are available –The amount of privilege

7.5 Backward Compatibility Backward compatible with a previous model –Intel 8086 –80186 –80286 –80386 –80486 –pentium

7.6 Changing Modes There are two ways –Automatic (initiated by hardware) –Manual (under program control) Three mechanisms –An instruction to set the current mode –Store a value into the mode register –A change occur as the side effect of another instruction

7.7 Privilege and Protection Part of the current mode specifies the level of privilege –Before it executes an application program, an operating system changes the mode to reduce privilege

7.8 Multiple Levels of Protection By using a protection scheme to limit the operations that are allowed, a CPU can detect attempts to perform unauthorized operations

7.9 Micro-coded Instructions

From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved.

7.10 Microcode Variations Microcode implements the entire fetch- execute cycle –Greater flexibility, lower performance Only uses microcode for extensions –A vender can manufacture minor variations of the basic CPU

7.11 The Advantage of Microcode Less prone to errors Take less time Easier to update

The disadvantage of Microcode More overhead The micro controller must run at much higher speed The cost of a macro instruction depends on the micro instruction set

7.12 Making Microcode Visible to Programmer Some CPU provide a mechanism that allows microcode to be rewritten The CPU’s owner can create a macro instruction set that is optimized for a specific task

7.13 Vertical Microcode The microcontroller follows the same general approach used for conventional processors The micro controller used in a CISC processor can consist of a small, fast RISC processor

7.14 Horizontal Microcode The CPU hardware consists of multiple functional units, and each unit is controlled independently Horizontal microcode allows the hardware to run faster, but is more difficult to program

From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved.

7.15 Example Horizontal Microcode Each functional unit is controlled by a set of wires that carry commands The unit can be controlled by a single binary value –One causes the unit to send the current content –Zero causes the unit to stop interaction

From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved.

7.16 A Horizontal Microcode Example Move r4, opnd1 Move r13, opnd2 Add Move res2, r4

From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved.

7.17 Operations That Require Multiple Cycles A programmer must ensure that each unit is given the correct amount of times to complete its task An instruction can be inserted to add delay processing

From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved.

7.18 Horizontal Microcode and Parallel Execution Parallelism is possible because the underlying hardware contains units that operate independently. An instruction can simultaneously moves a new value into an operand unit while an ALU operation continues

From Essentials of Computer Architecture by Douglas E. Comer. ISBN © 2005 Pearson Education, Inc. All rights reserved.

7.19 Look-ahead and High Performance Execution An intelligent controller looks ahead at the instructions, finds values that will be needed, and direct functional units to start fetching or computing the values. If the CPU contains enough functional units, an intelligent controller can schedule all independent macro instructions to be executed.

7.20 Parallelism and Execution Order The controller must balance between two goals : –Maximize the amount of parallel evaluation –Preserve the original sequential semantics

7.21 Out-of Order Instruction Execution To achieve highest speed, a modern CPU contains multiple copies of functional units that permit multiple instructions to be executed simultaneously. An intelligent controller schedules execution in an order that preserves the appearance of sequential processing.

7.22 Conditional Branches and Branch Prediction A CPU that offers parallel instruction execution can handle conditional branches by proceeding to pre-compute values on one or both branches, and choosing which values to use when the computation of the branch condition completes.

7.23 Consequences for Programmers A programmer can optimize performance by arranging code so that the most common cases take the branch.