Integration of Photonic Functions in and with Silicon Roel Baets Wim Bogaerts, Pieter Dumon, Günther Roelkens, Ilse Christiaens, Kurt De Mesel, Dirk Taillaert, Bert Luyssaert, Joris Van Campenhout, Peter Bienstman, Dries Van Thourhout, Vincent Wiaux, Johan Wouters, Stephan Beckx Ghent University and IMEC

Outline why Silicon photonics? sub-micron photonics in Silicon? heterogeneous integration of III-V components onto Silicon?

Evolution of electronics... (IBM, mark1) 5 tons of components can multiply in 1 sec (pentium 4) 42 million transistors 2000 000 000 multiplications in 1 sec

Success of electronics? Integrated circuits economics of wafer scale integration performance (smaller is faster!) miniaturization in its own right complex function can be made by a limited number of high-yield processes focus on one production technology few companies in the food chain all efforts on the same material = Silicon

Should we integrate in photonics? Yes! there are good reasons to do so economics of wafer scale integration performance miniaturization integrate with electronics reduce costly optical packaging!!! optical packaging is expensive! (often requires manual and/or active alignment at (sub)-micron level) more integration = less packaging

The key bottleneck of photonic integration (By far too) many degrees of freedom many different materials many different component types many different wavelength ranges Hence: no generic integration technology for many different applications no high volume technology platforms too high cost Integration is not an industrial reality (yet)

The way out - a roadmap 1. Use mainstream Silicon(-based) technology wherever possible, CMOS fab compatible otherwise, use dedicated Silicon fab 2. Add other materials where needed for specialty functions if the added value motivates it 3. By using wherever possible : wafer-scale post-processing technology (build-up) otherwise, die-scale technology 4. Build a photonic IC industry on this basis

Silicon-based photonic components and ICs Many examples: detector arrays and solar cells CCD and CMOS-based image sensors micro-displays MEMS devices LEDs Silica-on-Silicon passive photonic ICs

CCD and CMOS-based image sensors Several million pixels High volume applications

Liquid Crystal microdisplay on CMOS design by TFCG-IMEC Mosarel-project

MEMS based microdisplays DLP: Digital light processing DMD: Digital Mirror Device Greyscale: by fast on-off switching Color: time multiplexing 16umx16um pixels 2 million micromirrors Advantage: - higher brightness - better surface coverage than LCD www.dlp.com Digital Light Processing (DLP) Digital Mirror Device (DMD)

2D Crossconnects

3-D CrossConnect Lucent Technologies, Bell Labs http://www.bell-labs.com/org/physicalsciences/projects/mems/mems.html 2-axis – angular range of > 6degree Continuous, controlled tilt 238x238 demonstrated Average loss: 1.3dB (max 2dB) Crosstalk: better -40dB PDL: 0.1 dB Lucent Technologies, Bell Labs

Efficient Silicon-based LEDs announced October 2002 by Salvo Coffa’s research team at ST Microelectronics light emission from: SiO2 layer, between p- and n-type Silicon doped with rare earth ions by standard ion implantation made conductive by Si nanoscale particles (1-2nm) emission wavelength: Cerium: blue Terbium: green Erbium: 1.55 micron as efficient as III-V LEDs next step: a laser???

Silica on Silicon Arrayed Waveguide Grating -(de)multiplexer (AWG) Lucent Si-wafer doped SiO2 or SiOxNy SiO2

“Group IV photonics” 1st International Conference on Hongkong 29 September – 1 October 2004 Organized by IEEE-LEOS

Outline why Silicon photonics? sub-micron photonics in Silicon? heterogeneous integration of III-V components onto Silicon?

Scale difference Wavelength-scale photonics Wavelength-scale photonics Electronics interconnects gate width transistor flip-flop Active opto-electronics detector Wavelength-scale photonics LED stripe laser VCSEL 2R regenerator taper spot-size convertor Passive photonics fibre core Wavelength-scale photonics linewidth in current PIC AWG in Silica on Silicon Bend radius 1cm 1mm 100m 10m 1m 100nm

Reduce PIC-size / increase density WE NEED: Ultra-compact waveguiding with Sharp bends (Bend radius < 10m) Compact splitters and combiners Short mode-conversion distances Compact wavelength selective functions Highly dispersive element Small, high-Q resonators Compact non-linear functions Increase power density by using tight confinement

High refractive index contrast (>2:1) contrast allows for: very tight bends compact resonators with low loss wide angle mirrors very compact mode size --> strong field strength --> strong non-linear effects --> small volume to be pumped in active devices --> faster and/or lower power photonic bandgap effects  high refractive index contrast is the key for ultra-compact photonic circuits semiconductor air dielectric

Silicon-on-Insulator Transparent at telecom wavelengths (1.55m and 1.3m) High refractive index contrast in-plane: 3.45(Si) to 1.0 (air) out-of-plane: 3.45 (Si) to 1.45 (SiO2) Compatible with CMOS processes Si substrate silica Silicon

Ultra-compact waveguide candidates Photonic Crystal waveguides: in-plane: high contrast photonic crystal defect out-of-plane: TIR Photonic Wires: in-plane: high contrast TIR out-of-plane: TIR

Guided Bloch mode conditions  M K  Radiation leak into substrate Coupling forw/backw Waveguide PBG guiding by PhC & SWG PBG Light line Guided Bloch Mode WG mode leak into PhC x y z p/a GM x z y GK p/a Brillouin Zone

Compact bends Photonic Crystal Photonic Wire Light is confined by the PBG Photonic Wire Deep etch allows for short bend radius (a few m) Corner mirrors

Spectral accuracy and geometrical accuracy High index contrast components: - interference based filters, with d the waveguide width () - cavity resonance wavelength with d the cavity length (a few ) - photonic crystal with d the hole diameter () if tolerable wavelength error : 1 nm  tolerable length scale error : (of the order of) 1 nm

Ultra-compact waveguide candidates Photonic Crystal waveguides: in-plane: high contrast photonic crystal defect out-of-plane: TIR Photonic Wires: in-plane: high contrast TIR out-of-plane: TIR Both cases: feature size : 50-500 nm required accuracy of features: 1-10 nm NANO-PHOTONIC waveguides

Deep UV Lithography for CMOS 248nm excimer laser Lithography ASML PAS 5500/750 Step-and-scan Automated in-line processing (spin-coating, pre- and post-bake, development) 4X reticles Standard process 193nm excimer laser Lithography ASML PAS 5500/1100 Step-and-scan

Fabrication with deep UV Litho Photoresist AR-coating Photoresist Si-substrate SiO2 Si Bare wafer Photoresist (UV3) Soft bake AR coating Illumination (248nm deep UV) Post bake Development Resist trim Silicon etch Resist strip W. Bogaerts et al. Opt. Exp. 12(8) p.1583

Fabricated Structures

SOI photonic wires Shallow etch, TE w Propagation losses 400nm 440nm 33.8 9.4 7.4 2.4 ± 1.7 dB/cm ± 1.8 dB/cm ± 0.9 dB/cm ± 1.6 dB/cm Si substrate SiO2 1m Si w 220nm

Ring resonators in Silicon on Insulator 10m Photonic wire In Return bend ±2dB loss Through Drop Racetrack resonator 10m 3m

Racetrack Resonator Wire width = 510nm TE polarisation Q  12000 40% efficiency FSR=16.5nm Finesse=137 3.14m 4µm pass port -5 -10 -15 normalized transfer [dB] -20 -25 drop port -30 -35 1524 1524.5 1525 1525.5 1526 1526.5 PTL 16(5) pp.1328-1330 wavelength [nm]

AWG 5 x 8 AWG, 400GHz spacing, 8 Channels 300µm x 300µm area -8dB loss in star couplers - 6-10 dB crosstalk

Cascaded MZ Filter Example: 6 stage CMZ 3.2nm bandwidth 17nm FSR coupling efficiency ~80% -10 dB crosstalk pass normalized output [dB] drop gap width = 220nm waveguide width = 535nm wavelength [nm] waveguide width = 565nm L = 32.8µm 20µm 14µm 20µm 20µm 14µm 20µm

Outline why Silicon photonics? sub-micron photonics in Silicon? heterogeneous integration of III-V components onto Silicon?

Integration of active components light emitters with high efficiency and high modulation bandwidth  III-V semiconductors compact optical amplifiers  III-V semiconductors high speed detectors (in particular in IR)  III-V semiconductors high speed + compact optical modulators and switches  III-V semiconductors

Integration of active + passive photonics Integration of active photonics and electronics The options: monolithic in III-V complex and costly Silicon-based IC + hybridly mounted III-V components costly + yield problem

Integrating electronics and photonics 2 4x8 VCSEL arrays 2 4x8 Detector arrays FPGA CMOS circuit + drivers + receivers

Integration of active + passive photonics Integration of active photonics and electronics The options: monolithic in III-V complex and costly Silicon-based IC + hybridly mounted III-V components costly + yield problem direct epitaxy of III-V on Silicon low III-V quality (so far) bonding of III-V membranes on Silicon wafers (electronic or passive photonic) infancy stage but looks promising

Bonded InP devices bonding substrate removal InP wafer SOI wafer

Bonding technologies Direct bonding (e.g. wafer fusion) Metallic bonding (e.g. with solder) Bonding with intermediate ‘glue’ layer e.g. BCB, SOG …

Silica-Silica bonding Future: automated bonding of multiple InP dies to Silicon and subsequent substrate removal

BCB-bonding technology Process Cleaning of the wafers Spinning of BCB Bonding on a hot plate Curing (250 o C, 1h) Substrate removal mechanical thinning (polishing) chemical thinning Bonding layer thickness > 1.5 um

Die-to-wafer bonding Large size difference between III-V wafers (2-6”) and Silicon-wafers (8-12”)  bonding of III-V islands on processed Silicon-wafer  bonding must be low-temperature process (<450C)  further wafer-scale processing of III-V devices after bonding Silicon electronics Silicon, passive micro-optics Silicon wafer III-V die, active micro-optics

InP membrane photonic crystal components Building blocks for photonic integration microcavities low threshold optically pumped photonic crystal microlasers single line defect waveguide Lyon- / Viktorovitch-LEOM CNRS/ LEOS 2002-glasgow

InP membrane laser diode Processing sequence: Si substrate BCB InP substrate Ti/Au contact Si substrate polyimide p-contact n-contact Si substrate top contact (n-contact) polyimide

InP membrane laser diode SEM photograph:

InP membrane laser diode Degradation tests: damp heat testing (85°C, 85% RH) for 48, 100, 250 and 500 hours PI IV Rs No observable degradation  Further indication of bonding quality

Application: FP6-PICMOS project GOAL: Build Photonic Interconnect Layer on CMOS by waferscale integration Solve CMOS interconnect bottleneck Use waferscale technologies, compatible with CMOS Coordination: Dries Van Thourhout, Ghent University-IMEC, Belgium CMOS-wafer Ultra-compact msources and mdetectors coupled to waveguides Photonic wiring layer based on high index-contrast SOI or polymer waveguides Goal of the PICMOS-project is to solve the ITRS “interconnect bottleneck” by adding photonic interconnect layer on top of next-generation CMOS-circuits. (interconnect bottleneck = problem on global interconnect level due to increasing RC-delay in next generation CMOS) The photonic interconnect layer will be built using using waferscale technologies and waferbonding. We will demonstrate feasibility and compatibility with CMOS processing technologies. Therefore we will develop ultra-compact InP-based sources and detectors. We aim for a footprint < 100um^2 (will be based on photonic crystal sources). The photonic interconnect circuit will either be based on high index contrast SOI-waveguides (by IMEC) or polymer waveguides (developed by ST) A systems workpackage is devoted to identify application domain and required specifications. A bonding workpackage will evaluate different approaches to obtain a industrially compatible die-to-wafer bonding technology. Partners: IMEC is prime-contractor. ST Microelectronics CEA-LETI TRACIT: Spin-off of CEA-LETI, works on waferbonding CNRS-FMNT: FMNT: Federation Micro et NanoTechnologie, group of CNRS-labs in neighbourhood of Lyon/Grenoble NCSR-D: National Centre Science Research Demokritos (Greece) TU/e : Technical University Eindhoven.

PICMOS Photonic Crystal Sources Membrane type Photonic Crystal Sources coupled to underlying waveguide Develop efficient electrical contacting scheme Footprint < 100mm2 – Ith < 1mA – Bandwidth > 10GHz III-V PC laser Si waveguide (C. Seassal – CNRS-FMNT-LEOM)

Conclusions Silicon-based photonics Silicon-based nanophotonics The power of Silicon technology brought to the world of photonics Silicon-based nanophotonics Ultra-compact passive photonic ICs made by means of CMOS-technology Active photonic components in III-V membranes bonded to Silicon Wafer-scale approach to the integration of Electronics Passive (nano)photonics Active (nano)photonics