Registers and Shift Registers Discussion D8.2. D Flip-Flop 0 0 1 1 1 0 X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive.

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Presentation transcript:

Registers and Shift Registers Discussion D8.2

D Flip-Flop X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

A 1-Bit Register

If LOAD = 1, then INP0 gets latched to Q0 on the rising edge of the clock, CLK

A 4-Bit Register

Implementing Registers in Verilog //A 4-bit register with asynchronous clear and load module reg4(Clk,Clear,Load,D,Q); input [3:0] D; input Clk,Clear,Load; output [3:0] Q; reg [3:0] Q; Clk or posedge Clear) if(Clear == 1) Q <= 0; else if(Load) Q <= D; endmodule

4-Bit Shift Register

shift4.v module ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= data_in; Q[2:0] <= Q[3:1]; end endmodule Note non-blocking assignment

shift4 simulation

Ring Counter

ring4.v module ring4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Ring Counter clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1]; end endmodule

ring4 simulation

Johnson Counter

module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Johnson Counter clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1]; end endmodule johnson4.v

Johnson Counter

A Random Number Generator

Q3 Q2 Q1 Q C E F B Q3 Q2 Q1 Q A D

module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Random number generator clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1]; end endmodule rand4.v

A Random Number Generator

clk inp Q2 Q0 Q1 outp Clock Pulse

module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp; wire outp; reg [2:0] Q; // clock pulse generator clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[2] <= inp; Q[1:0] <= Q[2:1]; end assign outp = Q[2] & Q[1] & ~Q[0]; endmodule clk_pulse.v

clk inp Q2 Q0 Q1 outp